View TMP92FD54AIF_4469127.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

2006-01-27 92fd54ai-1 tmp92fd54ai cmos 32-bit micro-controller TMP92FD54AIF 1. outline and device characteristics tmp92fd54ai is high-speed advanced 32-bit micro-controller developed for controlling equipment which processes mass data. tmp92fd54ai is a micro-controller which has a high-performance cpu (900/h1 cpu) and various built-in i/os. tmp92fd54ai is housed in a 100-pin mini flat package. device characteristics are as follows: (1) cpu : 32-bit cpu(900/h1 cpu) compatible with tlcs-900,900/l,900/l1,900/h,900/h2?s instruction code 16mbytes of linear address space general-purpose register and register banks micro dma : 8channels (250ns / 4bytes at fc = 20mhz, best case) minimum instruction execution time : 50ns(at 20mhz) internal data bus : 32-bit (2) internal memory internal ram : 32k-byte internal rom : 512k-byte flash e2prom 3k-byte mask rom (for flash boot mode)
2006-01-27 92fd54ai-2 tmp92fd54ai (3) external memory expansion 16m-byte linear address space (memory mapped i/o) external data bus : 8bit(for external i/o expansion) * can?t use upper address bus when built-in i/os are selected (4) memory controller (memc) chip select output : 1 channel (5) 8-bit timer : 8 channels 8-bit interval timer mode (8 channels) 16-bit interval timer mode (4 channels) 8-bit programmable pulse generation (ppg) output mode (4 channels) 8-bit pulse width modulation (pwm) output mode (4 channels) (6) 16-bit timer : 2 channels 16-bit interval timer mode 16-bit event counter mode 16-bit programmable pulse generation (ppg) output mode frequency measurement mode pulse width measurement mode time differential measurement mode (7) serial interface (sio) : 2 channels i/o interface mode universal asynchronous receiver transmitter (uart) mode (8) serial expansion interface (sei) : 1 channel baud rate 4/2/0.5mbps at fc=20mhz. (9) serial bus interface (sbi) : 3 channels clocked-synchronous 8-bit serial interface mode i 2 c bus mode (10) can controller : 1channel supports can version 2.0b. 16 mailboxes (11) 10-bit a/d converter (adc) : 12 channels a/d conversion time 8sec @fc=20mhz. total tolerance +/- 3lsb (excluding quantization error) scan mode for all 12channels (12) watch dog timer (wdt) (13) timer for real-time clock (rtc) can operate with only low frequency oscillator. (14) interrupt controller (intc) : 60 interrupt sources 9 interrupts from cpu 42 internal interrupt vectors 9 external interrupt vectors (15) i/o port : 68pins (16) standby mode four modes : idle3,idle2,idle1 and stop stop mode can be released by 9 external inputs. (17) internal voltage detection flag (ramstb)
2006-01-27 92fd54ai-3 tmp92fd54ai (18) power supply voltage vcc5 = 4.5v to 5.25v vcc3 = 3.3v (vcc3 connect to regout; built-in voltage regulator.) (19) operating temperature : -40 to 85 degree c (20) package : p-lqfp100-1414-0.50c
2006-01-27 92fd54ai-4 tmp92fd54ai figure 1 tmp92fd54ai block diagram port0 port4 interrupt controller serial bus i/f channel 0 serial bus i/f channel 1 serial exp.i/f pm0 ( ss / a8 ) pm1(mosi/a9) pm2(miso/a10) pm3(seclk/a11) pn0(sck0) pn1(so0/sda0) pn2(si0/scl0) pn3(sck1/a12) pn4(so1/sda1/a13) pn5(si1/scl1/a14) p00top07 ( d0tod7 ) p40top47 (a0toa7) int0 nmi reset a m 0 a m1 test0 test1 port7 p70 ( rd ) p71 ( wr ) p73( cs ) p74 p75 ( wait ) clk ix iy iz sp l h e d c b a w xsp xiz xiy xix xhl xde xbc xwa 900/h1 cpu f sr 32 bits p c 32kb ram 512kb flash e2prom serial i/o channel 0 serial i/o channel 1 10-bit 12ch a/d converter 8bit timer (timer0) 8bit timer ( timer1 ) 8bit timer (timer2) 8bit timer ( timer3 ) 8bit timer (timer4) 8bit timer ( timer5 ) 8bit timer (timer6) 8bit timer ( timer7 ) can controller watch-dog timer 16bit timer (timer8) 16bit timer (timera) real time clock (rtc) osc rtc regulator (to7/int4)pc5 (ti4/int3)pc3 (to3/int2)pc2 (to5)pc4 (ti0/int1)pc0 (to1)pc1 ( tx ) pf6 ( rx ) pf7 vrefl vrefh a dvss advcc pg0topg7 ( an0toan7 ) pl0topl3 ( an8toan11 ) ( rxd 0 ) pf1 (txd0)pf0 (rxd1)pf4 ( txd1 ) pf3 (sclk0/ cts0 )pf2 (sclk1/ cts1 )pf5 (ti8/wuint0/int5/a16) pd 0 (ti9/wuint1/int6/a17) pd1 (to8/wuint2/a18) pd2 (to9/wuint3/a19) pd3 (tia/wuint4/int7/a20) pd4 ( tib/wuint5/a21 ) pd5 (toa/wuint6/a22) pd6 (tob/wuint7/a23) pd7 regout xt1 xt2 x1 x2 dvss[6] dvcc5[5] regen dvcc3[3] connect serial bus i/f channel 2 pm4(sck2) pn6(so2/sda2/a15) p72(si2/scl2) 3k-byte mask rom (for flash boot mode)
2006-01-27 92fd54ai-5 tmp92fd54ai 2. pin assignment and functions 2.1 pin assignment pl3/an11 pl2/an10 pl1/an9 pl0/an8 pg7/an7 pg6/an6 pg5/an5 pg4/an4 pg3/an3 pg2/an2 pg1/an1 pg0/an0 dvss p75/wait dvcc3 p74 p73/cs p72/si2/scl2 p71/wr p70/rd am0 reset am1 clk test0 TMP92FD54AIF (p-lqfp100-1414-0.50c) 14 x 14 x 1.4 top view dvcc5 x1 dvss x2 test1 xt1 xt2 dvcc3 pn6/so2/sda2/a15 pn5/si1/scl1/a14 pn4/so1/sda1/a13 pn3/sck1/a12 dvss pn2/si0/scl0 dvcc5 pn1/so0/sda0 pn0/sck0 pc0/ti0/int1 pc1/to1 pc2/to3/int2 pc3/ti4/int3 pc4/to5 pc5/to7/int4 regen dvss d6/p06 d7/p07 a0/p40 a1/p41 a2/p42 a3/p43 a4/p44 a5/p45 a6/p46 a7/p47 dvcc3 int0 dvss nmi dvcc5 a16/wuint0/int5/ti8/pd0 a17/wuint1/int6/ti9/pd1 a18/wuint2/to8/pd2 a19/wuint3/to9/pd3 a20/wuint4/int7/tia/pd4 a21/wuint5/tib/pd5 a22/wuint6/toa/pd6 a23/wuint7/tob/pd7 regout dvcc5 advss a dvcc vrefl vrefh rx/pf7 tx/pf6 cts1/sclk1/pf5 rxd1/pf4 txd1/pf3 cts0/sclk0/pf2 rxd0/pf1 txd0/pf0 dvss pm4/sck2 dvcc5 a 8/ss/pm 0 a 9/mosi/pm1 a 10/miso/pm2 a 11/seclk/pm 3 d0/p0 0 d1/p01 d2/p02 d3/p03 d4/p04 d5/p05 0 1 0 5 10 15 20 25 75 70 65 60 55 51 50 45 40 35 30 26 0 76 0 80 0 85 0 90 0 95 100
2006-01-27 92fd54ai-6 tmp92fd54ai 2.2 pin names and functions the following table shows the names and functions of the input/output pins. pin name pin number number of pins in/out function (cmos) p00..p07 d0..d7 20 th ?27 th 8 (ttl) in/out in/out port 0: i/o port. input or output specifiable in units of bits. data: data bus 0 to 7. p40..p47 a0..a7 28 th ?35 th 8 in/out out port4: i/o port. input or output specifiable in units of bits. address: address bus 0 to 7. p70 rd 81 st 1 in/out out port70: i/o port. read: outputs strobe signal to read external memory. p71 wr 82 nd 1 in/out out port 71: i/o port. write: output strobe signal to write external memory. p72 si2 scl2 83 rd 1 in/out port 72: i/o port. sbi channel 2: input data at sio mode sbi channel 2: clock input/output at i2c mode p73 cs 84 th 1 in/out out port 73: i/o port. chip select: outputs ?low? if address is within specified address area. p74 85 th 1 in/out port 74: i/o port. p75 wait 87 th 1 in/out in port 75: i/o port. wait: signal used to request cpu bus wait. pc0 ti0 int1 58 th 1 in/out in in port c0: i/o port. timer input 0: input pin for timer 0. interrupt request pin 1: rising-edge interrupt request pin. pc1 to1 57 th 1 in/out out port c1: i/o port. timer output 1: output pin for timer 1. pc2 to3 int2 56 th 1 in/out out in port c2: i/o port. timer output 3: output pin for timer 3. interrupt request pin 2: rising-edge interrupt request pin. pc3 ti4 int3 55 th 1 in/out in in port c3: i/o port. timer input 4: input pin for timer 4. interrupt request pin 3: rising-edge interrupt request pin. pc4 to5 54 th 1 in/out out port c4: i/o port. timer output 5: output pin for timer 5. pc5 to7 int4 53 rd 1 in/out out in port c5: i/o port. timer output 7: output pin for timer 7. interrupt request pin 4: rising-edge interrupt request pin. pd0 ti8 int5 a16 wuint0 41 st 1 in/out in in out in port d0: i/o port. timer input 8: input pin for timer 8. interrupt request pin 5: interrupt request pin with programmable rising/falling edge. address: address bus 16. wake up input 0: wake up request pin with programmable rising, falling or both falling and rising edge. pd1 ti9 int6 a17 wuint1 42 nd 1 in/out in in out in port d1: i/o port. timer input 9: input pin for timer 9. interrupt request pin 6: rising-edge interrupt request pin. address: address bus 17. wake up input 1: wake up request pin with programmable rising, falling or both falling and rising edge. pd2 to8 a18 wuint2 43 rd 1 in/out out out in port d2: i/o port. timer output 8: output pin for timer 8 address: address bus 18. wake up input 2: wake up request pin with programmable rising, falling or both falling and rising edge. pd3 to9 a19 wuint3 44 th 1 in/out out out in port d3: i/o port. timer output 9: output pin for timer 9 address: address bus 19. wake up input 3: wake up request pin with programmable rising, falling or both falling and rising edge. int5 wuint0 int4 int3 int2 int1 int6 wuint1 wuint2 wuint3
2006-01-27 92fd54ai-7 tmp92fd54ai pin name pin number number of pins in/out function pd4 tia int7 a20 wuint4 45 th 1 in/out in in out in port d4: i/o port. timer input a: input pin for timer a interrupt request pin 7: interrupt request pin with programmable rising/falling edge. address: address bus 20. wake up input 4: wake up request pin with programmable rising, falling or both falling and rising edge. pd5 tib a21 wuint5 46 th 1 in/out in out in port d5: i/o port. timer input b: input pin for timer b. address: address bus 21. wake up input 5: wake up request pin with programmable rising, falling or both falling and rising edge. pd6 toa a22 wuint6 47 th 1 in/out out out in port d6: i/o port. timer output a: output pin for timer a. address: address bus 22. wake up input 6: wake up request pin with programmable rising, falling or both falling and rising edge. pd7 tob a23 wuint7 48 th 1 in/out out out in port d7: i/o port. timer output b: output pin for timer b. address: address bus 23. wake up input 7: wake up request pin with programmable rising, falling or both falling and rising edge. pf0 txd0 12 th 1 in/out out port f0: i/o port. serial interface channel 0: transmission data. pf1 rxd0 11 th 1 in/out in port f1: i/o port. serial interface channel 0: receive data. pf2 sclk0 cts0 10 th 1 in/out in/out in port f2: i/o port. serial interface channel 0: clock input/output. serial interface channel 0: data ready to send. (clear-to-send) pf3 txd1 9 th 1 in/out out port f3: i/o port. serial interface channel 1: transmission data. pf4 rxd1 8 th 1 in/out in port f4: i/o port. serial interface channel 1: receive data. pf5 sclk1 cts1 7 th 1 in/out in/out in port f5: i/o port. serial interface channel 1: clock input/output. serial interface channel 1: data ready to send. (clear-to-send) pf6 tx 6 th 1 in/out out port f6: i/o port. can: transmission data. pf7 rx 5 th 1 in/out in port f7: i/o port. can: receive data. pg0..pg7 an0..an7 89 th ?96 th 8 in in port g: input-only port. analog input 0 to 7: ad converter input pins. pl0..pl3 an8..an1 1 97 th ...100 th 4 in in port l0 to l3: input-only port. analog input 8 to 11: ad converter input pins. pm0 ss a8 16 th 1 in/out in out port m0: i/o port. sei: slave select input. address: address bus 8. pm1 mosi a9 17 th 1 in/out in/out out port m1: i/o port. sei: master output, slave input. address: address bus 9. pm2 miso a10 18 th 1 in/out in/out out port m2: i/o port. sei: master input, slave output. address: address bus 10. pm3 seclk a11 19 th 1 in/out in/out out port m3: i/o port. sei: clock input/output. address: address bus 11. pm4 sck2 14 th 1 in/out in/out port m4: i/o port. sbi channel 2: clock input/output at sio mode. pn0 sck0 59 th 1 in/out in/out port n0: i/o port. sbi channel 0: clock input/output at sio mode. int7 wuint4 wuint5 wuint6 wuint7
2006-01-27 92fd54ai-8 tmp92fd54ai pin name pin number number of pins in/out function pn1 so0 sda0 60 th 1 in/out out in/out port n1: i/o port. sbi channel 0: output data input/output at sio mode sbi channel 0: data input/output at i2c mode pn2 si0 scl0 62 nd 1 in/out in in/out port n2: i/o port. sbi channel 0: input data at sio mode sbi channel 0: clock input/output at i2c mode pn3 sck1 a12 64 th 1 in/out in/out out port n3: i/o port. sbi channel 1: clock input/output at sio mode address: address bus 12. pn4 so1 sda1 a13 65 th 1 in/out out in/out out port n4: i/o port. sbi channel 1: output data at sio mode sbi channel 1: data input/output at i2c mode address: address bus 13. pn5 si1 scl1 a14 66 th 1 in/out in in/out out port n5: i/o port. sbi channel 1: input data at sio mode sbi channel 1: clock input/output at i2c mode address: address bus 14 pn6 so2 sda2 a15 67 th 1 in/out out port n6: i/o port. sbi channel 2: output data at sio mode sbi channel 2: data input output at i2c mode address: address bus 15. nmi 39 th 1 in non-maskable interrupt: interrupt request pin with programmable falling or both falling and rising edge. int0 37 th 1 in interrupt request pin 0: interrupt request pin with programmable level or rising-edge. address mode pins: these pins are set as following, am0,1 80 th , 78 th 2 in (single-chip mode) (single-boot mode) am0 = l, am0 = h, am1 = h am1 = h test mode pins: these pins are set as following, test0,1 76 th , 71 st 2 in (single chip & single boot mode) test0 = l, test1 = l clk 77 th 1 out programmable clock output (with pull-up register). x1/x2 74 th , 72 nd 2 in/out oscillator connecting pins xt1/xt2 70 th , 69 th 2 in/out low frequency oscillator connecting pins. crystal or ceramic resonator is connected. rc oscillation is also possible depending on mask option. reset 79 th 1 in reset: initializes lsi (with pull-up register). vrefh 4 th 1 in ad reference voltage high vrefl 3 rd 1 in ad reference voltage low advcc 2 nd 1 - power supply pin for ad converter (+5v): connect advcc pin to 5v power supply. advss 1 st 1 - gnd pin for ad converter: connect advss pin to gnd (0v). dvcc5 15 th , 40 th , 50 th ,61 st ,75 th 5 - power supply pins (+5v): connect all dvcc5 pins to 5v power supply. dvcc3 36 th ,68 th ,86 th 3 - power supply pins (+3.3v): connect all dvcc3 pins to regout pin. dvss 13 th ,38 th ,51 st , 63 rd ,73 rd ,88 th 6 - gnd: connect all dvss pins to gnd (0v). regout 49 th 1 out regulator output 3.3v: connect capacitor to stabilize the regulator output. regen 52 nd 1 in regulator enable pin: should be set to h or open (with pull-up register). int 0 nmi
2006-01-27 92fd54ai-9 tmp92fd54ai 3. operation this section describes the basic components, functions and operation of tmp92fd54ai. 3.1 cpu tmp92fd54ai contains an advanced high-speed 32-bit cpu (900/h1 cpu) 3.1.1 cpu outline 900/h1 cpu is high-speed and high-performance cpu based on 900/h cpu. 900/h1 cpu has expanded 32-bit internal data bus to process instructions more quickly. outline of 900/h1 cpu are as follows: 900/h1 cpu width of cpu address bus 24-bit width of cpu data bus 32-bit internal operating frequency 16 to 20mhz (@f osc =8 to 10mhz) minimum bus cycle (internal ram) 1-clock access (50ns@f osc =10mhz) internal ram 32-bit 1-clock access internal rom 32-bit interleave 2-1-1-1-clock access 8/16-bit 2-clock access port, intc, memc internal i/o 8/16-bit 5 to 6-clock access sei, sio, wdt, 8-bit timer, 16-bit timer, rtc, 10-bit adc, sbi, can external device 8-bit 2-clock access (can insert some waits) minimum instruction execution cycle 1-clock(50ns@f osc =10mhz) conditional jump 2-clock(100ns@f osc =10mhz) instruction queue buffer 12-byte instruction set compatible with tlcs-900, 900/h, 900/l, 900/l1 and 900/h2 (normal, min, max and ldx instruction is deleted) micro dma 8-channels
2006-01-27 92fd54ai-10 tmp92fd54ai 4. functional description this section describes the hardware conf iguration of the tmp92fd54ai and how it operates. this device is a modified version of the tmp92cd54i with an internal 512k-byte flash memory instead of an internal 512k-byte mask rom. these internal ram are same size, 32k-byte. in all other respects the hardware configuration and the functionality of the tmp92fd54ai are identical to those of the tmp92cd54i. 4.1 flash memory 4.1.1 features 1) memory capacity tmp92fd54ai contains a 4-mbit (512k-byte) flash memory. this flash memory consists of 10 blocks (64 k-bytes 6 blocks, 56 k-bytes 2 blocks, 8 k-bytes 2 blocks), each of which can be independently protected from being programmed or erased. the cpu accesses the flash memory using a 32-bit wide data bus. a writer rewrites the flash memory in units of 16 bits. 2) flash memory access interleaved access (2-1-1-1-clock access) 3) program/erase time programming time (including verify):6 seconds per chip (typ.) 30 s per long word (typ.) erase time (including verify) 12 seconds per chip (typ.) note: the above values are typical times and do not include data transfer time. the actual time per chip varies according to the method used by the user to perform rewriting. 4) programming methods on-board programming mode, in which the memory can be rewritten while mounted on the user pcb. ? on-board programming mode 1) user boot mode supports user-defined rewriting methods. 2) single boot mode supports rewriting by serial transfer ( uni q ue to toshiba ) . 5) rewriting method with a few exceptions, the functions of the device?s internal flash memory conform to jedec standards. therefore, even if the user system uses flash memory as external memory, it can easily be adapted to use this lsi. furthermore, since the device?s flash memory has built-in circuits which can automatically write to the flash memory and erase the chip, the user does not have to code a program to perform the program and erase operations. the block protect function, which inhibits writing to or erasing the flash memory, only supports software protection (i.e. protection by a command setting), and does not support hardware protection (i.e. protection by the application of a voltage of 12 v).
2006-01-27 92fd54ai-11 tmp92fd54ai jedec-based functions functions which have been changed, added or removed auto program auto chip erase auto block erase data polling / toggle bit block protect (supports only software protection.) erase resume/suspend function 4.1.2 block diagram of the flash unit rom controller / interleave control mode set- up pin control address data flash memory column decoder / sense amp data latch address latch erase block decoder control circuit (including automatic sequence control circuit) command register rdy/bsy output internal address bus internal data bus internal control bus flash memory cell 512 kb row decoder mode control figure 4.1.1 block diagram of the flash unit
2006-01-27 92fd54ai-12 tmp92fd54ai 4.2 operation modes tmp92fd54ai has three operation modes. table 4.2.1 operation modes operation mode name description single-chip mode after a reset the device restarts from the internal flash memory. single-chip mode is further sub-divided into the following two modes: normal mode and user boot mode. the means for selecting between these two modes can be set by the user as desired. for example, it can be set so that if port 00 = 1, normal mode is selected, and if port 00 = 0, user boot mode is selected. the user application program must in corporate a routine to handle mode switching. normal mode the user?s application program is executed. user boot mode the flash memory on the user pcb board is rewritten. single boot mode after a reset the device starts up from the internal boot rom (the mask rom). the boot rom has an algorithm which allows memory on the user pcb to be rewritten via the device?s serial port. the internal flash memory can be rewritten by connecting the pcb to the external host via tmp92fd54ai?s serial port and transferring data using tmp92fd54ai data transfer protocol. of the modes listed in the table above, there are two operation modes in which the flash memory can be programmed: user boot mode and single boot mode. at user boot mode (in single-chip mode) and single boot mode, the internal flash memory can be rewritten while mounted on the user pcb. these two modes are collectively referred to as on-board programming mode.
2006-01-27 92fd54ai-13 tmp92fd54ai the input pin levels on am0, am1, test0 and test1, which are set externally during a reset, determine the operation mo de - either single-chip mode, single-boot mode. for all operation modes, the cpu will star t operating in the selected mode on completion of the reset. the input pin levels are set before the reset is completed. once the mode has been set, make sure that the input pin levels do not change during operation. the following table shows how each operation mode is set. the state diagram beneath the table shows the various possible mode transitions. table 4.2.2 operation mode pin settings input pins operation mode reset am1 am0 test1 test0 (1) single-chip mode (normal & user boot) 1 0 0 0 (2) single boot mode 1 1 0 0 figure 4.2.1 mode transition diagram 4.2.1 reset operation to reset the device, hold the reset input low (= 0) for at least 20 system clock periods while the power supply voltage is within the rated operating range and the internal high-frequency oscillator is os cillating stably. when the device is operating at 20 mhz, this period will by equal to 4 s. for details please refer to the section entitled reset operation in tmp92cd54i user?s manual. on-board programming mode / reset = 0 / reset = 0 (2) (1) switching set by the user single-chip mode reset state normal mode user boot mode single boot mode numbers in ( ) indicate the column row in the above table in which the input pin levels for the mode setting are shown.
2006-01-27 92fd54ai-14 tmp92fd54ai 4.2.2 memory map for each mode the memory map for the device varies according to the operation mode. the following diagram shows the memory map for each operation mode. figure 4.2.2 tmp92fd54ai memory map for each mode figure 4.2.3 block allocation single-chip mode single-boot mode 000000h 000400h 008400h f80000h ffff00h ffffffh fff000h 000000h 000400h 010000h 090000h fff400h ffff00h ffffffh 008400h ( s ) i flash rom internal i/o internal ram 32kb external memory internal flash rom 512kb internal i/o internal ram 32kb external memory external memory reserved internal boot rom 3kb internal flash rom 512kb (interrupt vector 256b) (interrupt vector 256b) block-0 block-1 block-2 block-3 block-4 block-5 block-6 block-7 block-8 block-9 64kb 64kb 64kb 64kb 64kb 64kb 56kb 56kb 8kb 8kb 512kb low high a ddress
2006-01-27 92fd54ai-15 tmp92fd54ai table 4.2.3 block address range by mode single-chip mode single-boot mode block-0 (64 kb) f80000h to f8ffffh 010000h to 01ffffh block-1 (64 kb) f90000h to f9ffffh 020000h to 02ffffh block-2 (64 kb) fa0000h to faffffh 030000h to 03ffffh block-3 (64 kb) fb0000h to fbffffh 040000h to 04ffffh block-4 (64 kb) fc0000h to fcffffh 050000h to 05ffffh block-5 (64 kb) fd0000h to fdffffh 060000h to 06ffffh block-6 (56 kb) fe0000h to fedfffh 070000h to 07dfffh block-7 (56 kb) fee000h to ffbfffh 07e000h to 08bfffh block-8 ( 8 kb) ffc000h to ffdfffh 08c000h to 08dfffh block-9 ( 8 kb) ffe000h to ffffffh 08e000h to 08ffffh
2006-01-27 92fd54ai-16 tmp92fd54ai 4.3 on-board programming mode (user-boot and single-boot) on-board programming mode allows flash memory to be rewritten while it is mounted on the user?s target system board. there ar e two versions of this mode: single boot mode, which supports the toshiba proprietary method of rewriting via serial i/o, and user boot mode (in single-chip mode), which allows user-defined rewriting methods to be defined in single-chip mode. 4.3.1 user boot mode (in single-chip mode) user boot mode enables a user-defined flash memory rewrite routine to be used. this mode is used when the data transfer bus which the user application flash memory rewrite program uses is not serial. rewriting is performed in single-chip mode. for this reason the operation mode within single-chip mode must be changed, from normal mode (the mode in which the user application program normally operates) to user boot mode, in which mode the flash memory can be rewritten. this requires that a condition-judging program be incorporated into the user application reset-processing program. any mode-switching condition may be set using the device?s i/os as long as it is suitable for the user system. also, the user?s exclusive flash memory rewrite routine, for use in user boot mode, may be programmed into the user application in advance, so that it can be used to rewrite the flash memory after the device has entered user boot mode. furthermore, since the processor cannot read data from the internal flash memory during an erase/program operation, the rewrite routine must be stored somewhere outside the flash memory so that it can be executed. while the on-chip flash memory is being rewritten in user boot mode, all interrupts including the non-maskable interrupt must be disabled. the pages which follow explain the procedure for rewriting the flash memory using two example case studies. in one case the rewrite routine is put into the internal flash memory (1-a); in the other the rewrite routine is transferred from an external source (1-b). for details of how to program/erase the flash memory, refer to section 4.4, programming/erasing flash memory during on-board programming.
2006-01-27 92fd54ai-17 tmp92fd54ai user boot mode (1-a) example procedure in which the rewrite routine is stored in the internal flash memory (step 1) first, the conditions (e.g. the pin status) under whic h the program will enter user boot mode must be set and the i/o bus which the program will use to transfer data must be selected. then a circuit must be designed and a corresponding program written. before mounting this device on the board, the following four programs must be written into one of the blocks of the flash memory using a programmer or similar device. (a) mode judgment routine: code to determine when rewriting of the device will commence (b) flash rewrite routine: code to read the rewrite data from an external source and then rewrite the flash memory (c) copy routine-1: code to copy (a) to (d) into the internal ram or to external memory (d) copy routine-2: code to copy (a) to (d) to the flash memory from the internal ram or the external memory. (step 2) the following explanation of the proceeding step assumes that the routines described above have been included in the reset-processing program. after a reset the reset-processing program must first determine whether or not the device should enter user boot mode. if the condition for entering user boot mode is true, the program must put the device into user boot mode, the mode in which the flash memory can be rewritten. (once the device has entered user boot mode, no interrupts ? not even nmis ? should be used.) (tmp92fd54ai) flash memory ram [reset-processing program] old user application program (controller) new user application program (i/o) (a) mode judgment routine (b) flash rewrite routine ( c ) cop y routine-1 (d) copy routine-2 (c) copy routine (tmp92fd54ai) flash memory ram [reset-processing program] old user application program (controller) new user application program (i/o) 0 1 reset condition for determining whether or not the device should be put into user boot mode (set by the user) (a) mode judgment routine (b) flash rewrite routine (c) copy routine-1 (d) copy routine-2
2006-01-27 92fd54ai-18 tmp92fd54ai (step 3) after the device has entered user boot mode, (c), the copy routine, must copy (a) to (d), the flash rewrite routine, into the internal ram or into external memory. (in the example shown below the routine is copied into the internal ram.) (step 4) the program jumps to the rewrite routine in ram, erases all blocks (chip-erase). (tmp92fd54ai) flash memory ram old user application program (controller) new user application program (i/o) [reset-processing program] (a) mode judgment routine (b) flash rewrite routine (c) copy routine-1 (d) copy routine-2 (a) mode judgment routine (b) flash rewrite routine (c) copy routine-1 (d) copy routine-2 (tmp92fd54ai) flash memory ram (controller) new user application program (i/o) (erased) (a) mode judgment routine ( b ) flash rewrite routine (c) copy routine-1 (d) copy routine-2
2006-01-27 92fd54ai-19 tmp92fd54ai (step 5) the copy routine-2 in the ram is executed and writes (a) to (d) into the flash memory. (step 6) next, the rewrite routine in the ram is executed and writes the new user application program into the erased area of the flash memory after loading it from the source of transfer (the controller ). (tmp92fd54ai) flash memory ram (controller) new user application program (i/o) (a) mode judgment routine (b) flash rewrite routine (c) copy routine-1 (d) copy routine-2 [reset-processing program] (a) mode judgment routine (b) flash rewrite routine (c) copy routine-1 (d) copy routine-2 (tmp92fd54ai) flash memory ram new user application program (controller) new user application program (i/o) (a) mode judgment routine (b) flash rewrite routine (c) copy routine-1 (d) copy routine-2 [reset-processing program] (a) mode judgment routine (b) flash rewrite routine (c) copy routine-1 (d) copy routine-2
2006-01-27 92fd54ai-20 tmp92fd54ai (step 7) the reset input pin must be driven low (= 0) to reset the device and to set it to normal mode. after de-assertion of the reset, the processor will start running the new user application program. (tmp92fd54ai) flash memory ram [reset-processing program] new user application program (controller) (i/o) 0 1 reset set to normal mode (a) mode judgment routine (b) flash rewrite routine (c) copy routine-1 (d) copy routine-2
2006-01-27 92fd54ai-21 tmp92fd54ai (1-b) example procedure for when the rewrite routine is transferred from an external source. (step 1) first, the condition (e.g. the pin status) under which the program will enter user boot mode must be set and the i/o bus which the program will use to transfer data must be selected. then a circuit must be designed and a corresponding program written. before mounting this device on the board, the following two programs must be written into one of the blocks of the flash memory using a programmer or similar device. (a) mode judgment routine: code to determine when rewriting of the device will commence (b) transfer routine: program for reading the rewrite program from an external source in addition, the programs shown below should be present in the host: (c) rewrite routine: program for rewriting the flash memory (d) copy routine-1: code to copy (a) to (d) into the internal ram or to the external rom. (e) copy routine-2 code to copy (a) to (d) into the flash memory from the internal ram or the external rom (step 2) the following explanation of the proceeding step assumes that the routines described above have been included in the reset processing program. after reset the reset-processing program must first determine whether or not the device should enter user boot mode. if the condition for entering user boot mode is true, the program must put the device into user boot mode, the mode in which to the flash memory can be rewritten. (once the device has entered user boot mode, no interrupts ? not even nmis ? should be used.) (tmp92fd54ai) flash memory ram [reset-processing program] (a) mode judgment routine old user application program (controller) (i/o) (b) transfer routine new user application program ( c ) rewrite routine (d) copy routine-1 (e) copy routine-2 (tmp92fd54ai) (controller) (i/o) 0 1 reset condition for determining whether or not the device should be put into user boot mode (set exclusively by the user) flash memory ram [reset-processing program] (a) mode judgment routine old user application program (b) transfer routine new user application program (c) rewrite routine (d) copy routine-1 (e) copy routine-2
2006-01-27 92fd54ai-22 tmp92fd54ai (step 3) after the device has entered user boot mode, (c) rewrite routine, (d) copy routine-1 and (e) copy routine-2, must be loaded from the source of transfer (the controller ) into the internal ram or into external memory using (b), the transfer routine. (in the example shown below the routine is copied into the internal ram.) (step 4) the program jumps to the copy routine-1 in ram, copy (a) and (b) into the internal ram or into external memory. (in the example shown below the routine is copied into the internal ram.). (tmp92fd54ai) flash memory [reset-processing program] (a) mode judgment routine old user application program (controller) (i/o) (b) transfer routine new user application program ( c ) rewrite routine (d) copy routine-1 (e) copy routine-2 ( c ) rewrite routine (d) copy routine-1 (e) copy routine-2 ram (tmp92fd54ai) flash memory [reset-processing program] (a) mode judgment routine old user application program (controller) (i/o) (b) transfer routine new user application program ( c ) rewrite routine (d) copy routine-1 (e) copy routine-2 ram ( c ) rewrite routine (d) copy routine-1 (e) copy routine-2 ( a ) mode j ud g ment routine ( b ) transfer routine
2006-01-27 92fd54ai-23 tmp92fd54ai (step 5) the rewrite routine in the ram is executed, erase all block of the flash memory (chip-erase). (step 6) the copy routine-2 in the ram is executed, copy (a) and (b) into the flash memory. (tmp92fd54ai) flash memory (controller) (i/o) (erased) ram ( c ) rewrite routine (d) copy routine-1 (e) copy routine-2 ( a ) mode j ud g ment routine ( b ) transfer routine new user application program ( c ) rewrite routine (d) copy routine-1 (e) copy routine-2 (tmp92fd54ai) flash memory [reset-processing program] (a) mode judgment routine (controller) (i/o) (b) transfer routine ram ( c ) rewrite routine (d) copy routine-1 (e) copy routine-2 ( a ) mode j ud g ment routine ( b ) transfer routine new user application program ( c ) rewrite routine (d) copy routine-1 (e) copy routine-2
2006-01-27 92fd54ai-24 tmp92fd54ai (step 7) next, the rewrite routine in the ram is executed and writes the new user application program into the erased area of the flash memory after loading it from the source of transfer (the controller ). (step 8) the reset input pin must be driven low (= 0) to reset the device and to set it to normal mode. after de-assertion of the reset, the processor will start running the new user application program. (tmp92fd54ai) (controller) (i/o) 0 1 reset set to normal mode flash memory ram [reset-processing program] (a) mode judgment routine new user application program (b) transfer routine (tmp92fd54ai) flash memory [reset-processing program] (a) mode judgment routine new user application program (controller) (i/o) (b) transfer routine ram ( c ) rewrite routine (d) copy routine-1 (e) copy routine-2 ( a ) mode j ud g ment routine ( b ) transfer routine new user application program ( c ) rewrite routine (d) copy routine-1 (e) copy routine-2
2006-01-27 92fd54ai-25 tmp92fd54ai 4.3.2 single-boot mode this mode involves activation of the internal boot rom (mask rom) so that the flash memory can be rewritten using a program stored in the boot rom. in this mode the internal boot rom is mapped into an area containing the interrupt vector table, in which the boot rom program is executed. the flash memory is mapped into an address space different from the one into which the boot rom is mapped (see figure 4.2.2 ). in single-boot mode the flash memory is rewritten by serial transfer of commands and data. first, the device?s sio (sio1) and the external host are connected and the rewrite program is copied from the external host into the device?s internal ram; the rewrite program is then executed in ram and the flash memory rewritten. the rewrite routine is initiated by sending commands and rewrite data from the host. the device must communicate with the host following the protocol described later. before the program can be transferred into ram, the user password is checked to ensure the security of the user rom data. if the password does not match, the program is not transferred into ram. interrupts must be disabled when peripheral functions such as the sio is utilized in single boot mode. nonetheless, the code for an interrupt cause is recorded in the intes1 register ; thus, for example, data receptions or transmissions in the sio can be confirmed by keeping track of value changes of the intes1 register. the nmi interrupt must be disabled at this time. to prevent the contents of flash memory inadvertently rewritten in single-chip mode (normal mode), it is recommended that, on completion of rewriting, write-protect be set for any blocks which the user wishes to protect. for details of how to program/erase the flash memory, please refer to section 4.4, programming/erasing flash memory during on-board programming.
2006-01-27 92fd54ai-26 tmp92fd54ai single boot mode (2-a) using the rewrite algorith m in the internal boot rom (step 1) the state of the flash memory is not important; it may contain the old version of the user program or it may have been erased. since the rewriting routine and rewrite data are transferred via sio (sio1), the device?s sio (sio1) and the external controller should be connected on the board. the user must ensu re that (a), the rewrite routine, is present on the controller . (step 2) to turn the boot rom on, reset must be de-asserted by setting the input pins accordingly. (a), the rewriting routine, must be transferred from the source (the controller) into the device via sio. before this is carried out, however, the password entered by the user must be checked agai nst the password registered on the user application program. (when the flash memory has been erased, erase data (?0xff?12byte ) is used as the password.) (tmp92fd54ai) flash memory ram contains old user application program (or has been erased). (controller) new user application program (i/o) (a) rewrite routine boot rom sio1 (tmp92fd54ai) (controller) (i/o) 0 1 reset new user application program (a) rewrite routine flash memory ram old user application program (or erased) boot rom sio1
2006-01-27 92fd54ai-27 tmp92fd54ai (step 3) after the password has been checked, (a), the rewrite routine, must be transferred from the source (the controller). the boot rom then loads the routine into the internal ram. it must be ensured, however, that the routine is stored within the ram address area 000400h to 006bffh. (step 4) the cpu jumps to (a), the rewrite routine, in ram and the rewrite routine erases the old user application program area (all the blocks at once). (tmp92fd54ai) flash memory ram old user application program (or erased) (controller) new user application program (i/o) (a) rewrite routine boot rom sio1 (a) rewrite routine (tmp92fd54ai) flash memory ram (controller) new user application program (i/o) (a) rewrite routine boot rom sio1 (a) rewrite routine erased
2006-01-27 92fd54ai-28 tmp92fd54ai (step 5) next, the rewrite routine in the ram is exec uted and writes the new user application program into the erased area of the flash me mory after loading it from the source of transfer (the controller). when the processor has finished writing the new user application program, write-protect for the user program area should be turn on. in the example below the rewrite data is transferred from the same host via the same sio as the rewrite routine. however, once normal program operation has started in ram, any other data bus and any other transfer source may be used as desired. the user must design the board hardware and write the rewrite routine accordingly. (step 6) when writing to the device has been completed, turn the power to the board off and remove the cable connecting the device and host. to execute the new user application program, turn the power back on again and st art the device in single-chip mode (normal mode). (tmp92fd54ai) (controller) 0 1 reset set for single-chip mode (normal mode) flash memory ram new user application program boot rom sio1 (tmp92fd54ai) flash memory ram new user application program (controller) new user application program (i/o) (a) rewrite routine boot rom sio1 (a) rewrite routine
2006-01-27 92fd54ai-29 tmp92fd54ai (1) typical connection scheme for single boot mode in single boot mode the flash memory is rewritten by means of a serial transfer. therefore on-board programming is carried out by connecting the device?s sio (channel1) and the controller (the programming tool) and sending commands from the controller to the target board. figure 4.3.1 shows an example connection scheme for a programming controller and a target board. figure 4.3.1 example of connection board and external controller in single boot mode (with communication via uart) reg. rom ram mode control for prog. controller v cc (5 v) v cc mode control for mcu mcu rs232c pc supply voltage dv cc (5 v) am1 (78 pin) dvcc (3.3 v) reset (79 pin) am0 (80 pin) reset am0 boot mode selection circuit rxd1 (8 pin) txd1 (9 pin) test1 (71 pin) test0 (76 pin) dv ss rx tx v ss v cc note) programming controller target board reg.
2006-01-27 92fd54ai-30 tmp92fd54ai (2) mode settings before on-board programming can be performed, the device must be started up in single boot mode. the input pins must be set as follows in order to start the device up in single boot mode. am0 = 1 am1 = 1 test0 = 0 test1 = 0 reset = 0 1 set the reset input pin low (= 0) and set the am0, am1, test0 and test1 pins as shown above. then de-assert reset (i.e. set it to 1). the device will start up in single boot mode. (3) memory map figure 4.3.2 compares the memory maps for single-chip mode and single-boot mode. as shown, in single-boot mode the internal flash memory is mapped into 010000h to 08ffffh. the boot rom (mask rom) is mapped into fff400h to ffffffh. figure 4.3.2 memory maps for single-chip mode and single-boot mode single-chip mode single-boot mode 000000h 000400h 008400h f80000h ffff00h ffffffh fff000h 000000h 000400h 010000h 090000h fff400h ffff00h ffffffh 008400h ( s ) i flash rom internal i/o internal ram 32kb external memory internal flash rom 512kb internal i/o internal ram 32kb external memory external memory reserved internal boot rom 3kb internal flash rom 512kb (interrupt vector 256b) (interrupt vector 256b)
2006-01-27 92fd54ai-31 tmp92fd54ai (4) interface specifications sio communication specifications for single boot mode are shown below. the device supports a serial operation mode: uart (asynchronous). before on-board programming can be executed, the programming controller must be set to the same communications format as the device side. ? communicating in uart mode communications channel: sio channel1 serial transfer mode: uart (asynchronous) mode, full-duplex communication data length: 8 bits parity bits: none stop bits: 1 baud rate: desired baud rate (see table 4.3.1(a) ) table 4.3.1(a) baud rate selection table baud rate (bps) 38400 19200 9600 4800 2400 table 4.3.1(b) pin connections pin uart dvcc (3.3 v) { power supply pins dvss { mode-setting pin am1, am0, test1, test0 { reset pin reset { txd1 { communications pins rxd1 { (5) data transfer format the operation commands and data transfer formats for each operation mode are shown in table 4.3.2 to table 4.3.67. for related information please refer to subsection (6), entitled boot program , on page 37 of section 4.3.2, single-boot mode . table 4.3.2 operation command data operation command data operation mode 10h ram transfer 20h flash memory sum 30h read product information 40h auto chip erase & unprotect
2006-01-27 92fd54ai-32 tmp92fd54ai table 4.3.3 single boot program transfer format (for ram transfer) number of bytes transferred data transferred from the controller to the device baud rate data transferred from the device to the controller boot rom 1st byte serial operation mode and baud rate settings for uart 86h desired baud rate (table 4.3.1(a)) ? 2nd byte ? ack response for serial operation mode for uart if normal (can be set) 86h (if the device determines that the baud rate cannot be set, it will stop operating.) 3rd byte operation command data (10h) ? 4rth byte ? ack response for operation command * 1 if normal 10h if abnormal 1h if communications error occurs 8h 5th byte 16th byte password data (12 bytes) (08fef4h to 08feffh) ? 17th byte checksum value for bytes 5 to 16 ? 18th byte ? ack response to checksum value * 1 if normal 10h if abnormal 11h if communications error occurs 18h 19th byte ram storage start address 31 to 24 ? 20th byte ram storage start address 23 to 16 ? 21st byte ram storage start address 15 to 8 ? 22nd byte ram storage start address 7 to 0 ? 23rd byte ram storage bytes 15 to 8 ? 24th byte ram storage bytes 7 to 0 ? 25th byte checksum value for bytes 19 to 24 ? 26th byte ? ack response for checksum value * 1 if normal 10h if abnormal 11h if communications error occurs 18h 27th byte mth byte ram storage data ? (m + 1) th byte checksum value for bytes 27 to m ? (m + 2) th byte ? ack response for checksum value * 1 if normal 10h if abnormal 11h if communications error occurs 18h ram (m + 3) th byte ? jump ram storage start address * 1: after returning an abnormal response the device waits for the operation command (third byte). in i/o interface mode this ack response is not generated. * 2: write your program so that the data in bytes 19 to 25 is stored within the ram address area 000400h to 0083ffh.
2006-01-27 92fd54ai-33 tmp92fd54ai table 4.3.4 boot program transfer format (for flash memory sum) number of bytes transferred data transferred from the controller to the device baud rate data transferred from the device to the controller boot rom 1st byte serial operation mode and baud rate settings for uart 86h desired baud rate (table 4.3.1(a)) ? 2nd byte ? ack response for serial operation mode for uart if normal (can be set) 86h (if the device determines that the baud rate cannot be set, it will stop operating.) 3rd byte operation command data (20h) ? 4th byte ? ack response for operation command * 1 if normal 20h if abnormal x1h if communication error occurs x8h 5th byte ? sum (upper) 6th byte ? sum (lower) 7th byte ? checksum value for bytes 5 to 6 8th byte (wait for the next operation command.) ? * 1: after returning an abnormal response the controller waits for the operation command (third byte).
2006-01-27 92fd54ai-34 tmp92fd54ai table 4.3.5 boot program transfer format (for reading product information) (1/2) number of bytes transferred data transferred from the controller to the device baud rate data transferred from the device to the controller boot rom 1st byte serial operation mode and baud rate settings for uart 86h ? 2nd byte ? desired baud rate (table 4.3.1(a)) ack response for serial operation mode for uart if normal (can be set) 86h (if the device determines that the baud rate cannot be set, it will stop operating.) 3rd byte operation command data (30h) ? 4th byte ? ack response for operation command * 1 if normal 30h if abnormal x1h if communication error occurs x8h 5th byte ? flash memory data (address 08fef0h) 6th byte ? flash memory data (address 08fef1h) 7th byte ? flash memory data (address 08fef2h) 8th byte ? flash memory data (address 08fef3h) 9th byte 20th byte ? product name (ascii code, 12 bytes) ?tmp92fd54ai ? beginning at the 9th byte 21st byte 24th byte ? password comparison start address (4 bytes) f4h, feh, 08h and 00h beginning at the 21st byte 25th byte 28th byte ? ram start address (4 bytes) 00h, 04h, 00h and 00h beginning at the 25th byte 29th byte 32nd byte ? ram user area end address (8 bytes) ffh, 6bh, 00h and 00h beginning at the 29th byte 33rd byte 36th byte ? ram end address (4 bytes) ffh, 83h, 00h and 00h beginning at the 33rd byte 37th byte 44th byte ? dummy data (8 bytes) 00h, 00h, 00h and 00h 00h, 00h, 00h and 00h 45th byte 46th byte ? dummy data (2 bytes) 00h and 03h beginning at the 45th byte 47th byte 50th byte ? flash memory start address (4 bytes) 00h, 00h, 01h and 00h beginning at the 47th byte 51st byte 54th byte ? flash memory end address (4 bytes) ffh, ffh, 08h and 00h beginning at the 51st byte 55th byte 56th byte ? flash memory block divisions information (2 bytes) 0ah and 00h beginning at the 55th byte 57th byte 60th byte ? start address of flash memory block of the same size (4 bytes) 00h, 00h, 01h and 00h beginning at the 57th byte
2006-01-27 92fd54ai-35 tmp92fd54ai table 4.3.6 boot program transfer format (for reading product information) (2/2) number of bytes transferred data transferred from the controller to the device baud rate data transferred from the device to the controller boot rom 61st byte 64th byte ? size (in half words) of flash memory blocks of the same size (4 bytes) 00h, 80h, 00h and 00h beginning at the 61st byte 65th byte ? number of flash memory blocks of the same size (1 byte) 06h 66th byte 69th byte ? start address of flash memory block of the same size (4 bytes) 00h, 00h, 07h and 00h beginning at the 66th byte 70th byte 73rd byte ? size (in half words) of flash memory block of the same size (4 bytes) 00h, 70h, 00h and 00h beginning at the 70th byte 74th byte ? number of flash memory blocks of the same size (1 byte) 02h 75th byte 78th byte ? start address of flash memory block of the same size (4 bytes) 00h, c0h, 08h and 00h beginning at the 75th byte 79th byte 82nd byte ? size (in half words) of flash memory block of the same size (4 bytes) 00h, 10h, 00h and 00h beginning at the 79th byte 83rd byte ? number of flash memory blocks of the same size (1 byte) 02h 84th byte ? checksum value for bytes 5 to 83 85th byte (wait for the next operation command data) ? * 1: after returning abnormal response, the device waits for the operation command (third byte).
2006-01-27 92fd54ai-36 tmp92fd54ai table 4.3.7 boot program transfer format (for auto chip erase & unprotect) number of bytes transferred data transferred from the controller to the device baud rate data transferred from the device to the controller boot rom 1st byte serial operation mode and baud rate settings for uart 86h desired baud rate (table 4.3.1(a)) ? 2nd byte ? ack response for serial operation mode for uart if normal (can be set) 86h (if the device determines that the baud rate cannot be set, it will stop operating.) 3rd byte operation command data (40h) ? 4th byte ? ack response for operation command * 1 if normal 40h if abnormal x1h if communication error occurs x8h 5th byte ? erase operation result response data if normal 4fh if abnormal 4ch 6th byte ? ack response if normal b1h if abnormal b4h 7th byte (wait for the next operation command.) ? * 1: after returning an abnormal response the controller waits for the operation command (third byte).
2006-01-27 92fd54ai-37 tmp92fd54ai (6) boot program when the device is turned on in single boot mode, the boot program starts up. these functions are detailed in the explanations ?1, ram transfer command? to ?4, auto chip erase & unprotect command) on the following pages. 1. ram transfer command ram transfer refers to the storing of data received from the controller in the device?s internal ram. if the transfer terminates normally, the boot program will start running the user program. the maximum size of the user program is 26kbytes, and the address at which program execution starts is the ram storage start address. this ram transfer function allows unique on-board programming by executing a rewrite program created by the user. in order for on-board programming to be executed as part of the user program, the flash memory command sequence described later in section 4.5 must be used. the ram transfer command examines the result of the password matching check before it starts operation. if the password is found not to match, ram transfer is not performed. once the ram transfer command has been completed, access to the entire on-chip ram is free. 2. flash memory sum command this command calculates the sum of 512 kbytes of flash memory and returns the result. there is no operation command available to the boot program which will enable it to read data from the entire area of the flash memory. instead, this flash memory sum command must be used. reading sum enables revision management of the application program to be carried out. 3. product information read command this command returns the product name, information about the device?s memory and various other details. specifically, this command returns data from a part of the flash memory area (addresses 08fef0h to 08fef3h). using this data as well as the above flash memory sum command enables revision management of the application program to be carried out. 4 auto chip erase & unprotect command this command erases all the blocks of flash memory. even when protect function is effective, all the blocks of flash memory are erased and protect function is initialized. it is not necessary to perform comparison of a password in this operation.
2006-01-27 92fd54ai-38 tmp92fd54ai 1) ram transfer command (see table 4.3.3.) 1. the data in the first byte is used to set the serial operation mode. for details of how to set the serial operation mode, please refer to part 6), entitled determination of serial operation mode , on page 47 of subsection 4.3.2 (6), boot program . if the serial operation mode is found to be uart mode, the device checks to see if the baud rate can be set. so uart receiving function needs to be disabled (sc1mod0 = 0) in the first byte. ? to communicate in uart mode send the data value 86h from the controller to the target board in uart mode at the desired baud rate. if the serial operation mode is found to be uart mode, the device checks to see whether the baud rate can be set. if the device finds that the baud rate cannot be set, it stops operation, and thus can no longer be communicated with. 2. the data in the second byte is the ack response returned by the device for the serial operation mode which is set by the data in the first byte. if the data in the first byte is found to signify uart mode and the baud rate can be set, the device will return 86h. ? uart mode the device checks to see if the baud rate can be set. if it is found that the baud rate can be set, the device rewrites the br1cr and br1add registers and returns 86h. if it is found that the baud rate cannot be set, the device stops operation and hence does not send any information. the controller sets a time-out time (5 seconds) after it has finished sending the first byte of data. if the data (86h) cannot be received normally within the time-out time, the device should be considered unable to communicate. reception is enabled (sc1mod0 = 1) before the data (86h) is written to the transmission buffer. 3. the data received in the third byte is the operation command data. in this case it is the data for the ram transfer command (10h). 4. the data in the fourth byte is the ack response data returned by the device for the operation command data in the third byte. the first, the device checks if the received data in the third byte contains an error. if a receive error is found, the device returns the ack response data for a communications error (bit 3) x8h and waits for the next operation command (third byte). the four high-order bits of the returned ack response data are undefined. (they are the four high-order bits of the immediately preceding operation command data.) next, if the data received in the third byte corresponds to one of the operation command values given in table 4.3.2, the device echoes back the received data (the ack response data for normal reception). in this case the data value 10h is echoed back and the program branches to the ram transfer processing routine. after branching to this routin e, the device checks the data in the password area. for details of how to check the data in the password area, refer
2006-01-27 92fd54ai-39 tmp92fd54ai to part 7), entitled the password , on page 50 of subsection 4.3.2 (6), boot program . if the received data does not correspond to any operation command, the device returns the ack response data for an operation command error (bit 0) x1h and waits for the next operation command (third byte). the four high-order bits of the returned ack response data are undefined. (they are the four high-order bits of the immediately preceding operation command data.) 5. the data received in bytes 5 to 16 is password data (12 bytes). the data in bytes 5 to 16 is compared with the data in flash memory address 08fef4h to 08feffh respectively. if the password does not match, the device sets the password error flag. 6. the data received as the 17th byte is checksum data. for details of how to calculate checksum data, please refer to part 9), entitled calculating checksum , on page 51 of subsection 4.3.2 (6), boot program . the checksum sent by the controller should be equal to the 2?s complement of the unsigned 8-bit value obtained by summing the value of bytes 5 to 16, ignoring any overflow. 7. the data in the 18th byte is the ack response data returned by the device for the data received as bytes 5 to 17 (the ack response for the checksum value). the device first checks to see whether the data received as bytes 5 to 17 contains any receive errors. if a receive error is found, the device returns the ack response data for a communications error (bit 3) 18h and waits for the next operation command (third byte). the four high-order bits of the returned ack response data are the four high-order bits of the immediately preceding operation command data, so the value of these bits is always 1. next, the device checks the checksum data in the 17th byte. this check is made to see if the low-order 8-bit value obtained by adding eight bits of the transmission data to bytes 5 to17 not including the sign (ignoring overflow) is 00h. if the value is not 00h, the device returns the ack response data for a checksum error (bit 0) 11h and waits for the next operation command (third byte). finally, the device examines the result of the password matching check. in the following cases the device returns ack response data for a password error (bit 0) 11h and waits for the next operation command (third byte). ? irrespective of the result of the password matching check for bytes 5 to 17, all 12 bytes of data in the password area will have the same value (a value other than ffh). ? none of the password data in bytes 5 to 17 matches the corresponding flash memory data. if all data is found to be normal as a result of the above check, the device returns the ack response data for normal reception, 10h. 8. the data received as bytes 19 to 22 indicates the start address in ram in
2006-01-27 92fd54ai-40 tmp92fd54ai which the block-transferred data is to be stored. the 19th byte corresponds to address bits 31 to 24 and the 22nd byte corresponds to address bits 7 to 0. 9. the data received as bytes 23 to 24 as bytes 19 to 22 the number of block-transferred bytes. the 23rd byte corresponds to bits 15 to 8 and the 24th byte to bits 7 to 0 of the transfer byte count. 10. the data received as the 25th byte is checksum data. the checksum data sent by the controller should be equal to the 2?s complement of the unsigned 8-bit value obtained by summing the values of bytes 19 to 24 ignoring any overflow. for details of how to calculate checksum data, please refer to part 9), entitled calculating checksum , on page 51 of subsection 4.3.2 (6), boot program . 11. the data in the 26th byte is the ack response data returned by the device for the data received as bytes 19 to 25 (the ack response for checksum value). the device first checks to see whether the data received as bytes 19 to 25 contains any receive errors. if a receive error is found, the device returns the ack response data for a communications error (bit 3) 18h and waits for the next operation command (third byte). the four high-order bits of the returned ack response data are the four high-order bits of the immediately preceding operation command data, so the value of these bits is always 1. next, the device checks the checksum data in the 25th byte. this check is made to see if the low-order 8-bit value obtained by adding eight bits of the transmission data to bytes 19 to 25 not including the sign (ignoring overflow) is 00h. if the value is not 00h, the device returns the ack response data for a checksum error (bit 0) 11h and waits for the next operation command (third byte). ? write your program so that the data in bytes 19 to 25 are stored within a ram address area from 000400h to 006bffh. if all data is found to go normal as a result of the above check, the device returns the ack response data for normal reception, 10h. 12. the data received as bytes 27 to m is the data which is to be stored in ram. this data is written to ram starting at the start address specified by the data received as bytes 19 to 22 and up until the number of bytes specified by the data received as bytes 23 to 24 in the 23rd to the 24th bytes has been reached. 13. the data received as the m + 1?th byte is checksum data. the checksum sent by the controller should be equal to the 2?s complement of the unsigned 8-bit value obtained by summing the values of bytes 27 to m, ignoring any overflow. for details of how to calculate checksum data, please refer to part 9), entitled calculating checksum , on page 51 of subsection 4.3.2 (6), boot program . 14. the data in the m + 2?th byte is the ack response data returned by the device for the data received as bytes 27 to m + 1 (the ack response for the checksum value). the device first checks to see whether the data received as bytes 27 to m + 1 contains any receive error. if a receive error is found, the
2006-01-27 92fd54ai-41 tmp92fd54ai device returns the ack response data for a communications error (bit 3) 18h and waits for the next operation command (third byte). the four high-order bits of the returned ack response data are the four high-order bits of the immediately preceding operation command data, so the value of these bits is always 1. next, the device checks the checksum data in the m + 1?th byte. this check is made to see whether the low-order 8-bit value obtained by adding eight bits of the transmission data to 27 to m + 1 bytes not including the sign (ignoring overflow) is 00h. if the value is not 00h, the device returns the ack response data for a checksum error (bit 0) 11h and waits for the next operation command (third byte). if all data is found to be normal as a result of the above check, the device returns the ack response data for normal reception, 10h. 15. if the ack response data in the (m + 2)th byte is a normal ack response, the device sends the normal ack response data 10h and then branches to the address specified by the data received as bytes 19 to 22.
2006-01-27 92fd54ai-42 tmp92fd54ai 2) flash memory sum command (see table 4.3.4.) 1. the transmitted/received data in the first and second bytes are the same as for the ram transfer command. 2. the data received in the third byte is the operation command data. in this case it is flash memory sum command data (20h). 3. the data in the fourth byte is the ack response data returned by the device for the operation command data in the third byte. the first, the device checks if the received data in the third byte contains an error. if a receive error is found, the device returns the ack response data for, communication error (bit 3) x8h and waits for the next operation command (third byte). the four high-order bits of the returned ack response data are undefined. (they are the four high-order bits of the immediately preceding operation command data.) next, if the data received in the third byte corresponds to one of the operation command values given in table 4.3.2, the device echoes back the received data (the ack response data for normal reception). in this case the data value 20h is echoed back and the program branches to the flash memory sum processing routine. if the received data does not correspond to any operation command the device returns the ack response data for an operation command error (bit 0) x1h and waits for the next operation command (third byte). the four high-order bits of the returned ack response data are undefined. (they are the four high-order bits of the immediately preceding operation command data.) 4. the data in the fifth and the sixth bytes sent by the device are the high-order and the low-order sum data respectively. for details of how to calculate sum, please refer to part 8), entitled calculating sum , on page 51 of subsection 4.2.2 (6), boot program . 5. the data in the seventh byte sent by the device is checksum data. this is the low-order 8-bit value in 2?s complement representation obtained by adding eight bits of transmit data in the fifth to the sixth bytes not including the sign (ignoring overflow). 6. the data received as the eighth byte is the data value for the next operation command.
2006-01-27 92fd54ai-43 tmp92fd54ai 3) product information read command (see table 4.3.5.) 1. the transmitted/received data in the first and second bytes are the same as for the ram transfer command. 2. the data received in the third byte is the operation command data. in this case it is product information read command data (30h). 3. the data in the fourth byte is the ack response data returned by the device for the operation command data in the third byte. the first, the device checks if the received data in the third byte contains an error. if a receive error is found, the device returns ack response data for a communication error (bit 3) x8h and waits for the next operation command (third byte). the four high-order bits of the returned ack response data are undefined. (they are the four high-order bits of the immediately preceding operation command data.) next, if the data received in the third byte corresponds to one of the operation command values given in table 4.3.2, the device echoes back the received data (the ack response data for normal reception). in this case the data value 30h is echoed back, and the program branches to the product information read processing routine. if the received data does not correspond to any operation command data, the device returns the ack response data for an operation command error (bit 0) x1h and waits for the next operation command (third byte). the four high-order bits of the returned ack response data are undefined. (they are the four high-order bits of the immediately preceding operation command data.) 4. the data in bytes 5 to 8 sent by the device is flash memory data (the data at addresses 08fef0h to 08fef3h). these addresses can be used to write id information for the software, facilitating version management. 5. the data in bytes 9 to 20 sent by the device denotes the product name. this data is ?tmp92fd54ai? and is transmitted as a sequence of ascii codes starting from the ninth byte. 6. the data in bytes 21 to 24 sent by the device is the password comparison start address. this data consists of the values f4h, feh, 08h and 00h and is transmitted starting from the 21st byte. 7. the data in bytes 25 to 28 sent by the device is the ram start address. this data consists of the values 00h, 04h, 00h and 00h and is transmitted starting from the 25th byte. 8. the data in bytes 29 to 32 sent by the device is the ram user area end address. this data consists of the values 006bffh and is transmitted starting from the 29th byte. 9. the data in bytes 33 to 36 sent by the device is the ram end address. this data consists of the values ffh, 83h, 00h and 00h and is transmitted starting from the 33rd byte.
2006-01-27 92fd54ai-44 tmp92fd54ai 10. the data in bytes 37 to 44 sent by the device is the dummy data. 11. the data in bytes 45 to 46 sent by the device is the dummy data 12. the data in bytes 47 to 50 sent by the device is the flash memory start address. this data consists of the values 00h, 00h, 01h and 00h and is transmitted starting from the 47th byte. 13. the data in bytes 51 to 54 sent by the device is the flash memory end address. this data consists of the values ffh, ffh, 08h and 00h and is transmitted starting from the 51st byte. 14. the data in bytes 55 to 56 sent by the device is the data which indicates how many blocks the flash memory is divided into. this data consists of the values 0ah and 00h and is transmitted starting from the 55th byte. 15. the data in bytes 57 to 92 sent by the device is the data containing information on flash memory blocks. with consecutive blocks of a given size starting at the flash memory start address comprising one unit, this information gives the start address of the first block, the size of the block (in half words) and the number of blocks in each unit of a given size. the data in bytes 57 to 65 sent by the device gives the above information for the 64k-byte blocks (block 0 to block 5). similarly, the data in bytes 66 to 74 gives the information for the 56k-byte blocks (block 6 and block 7), the data in bytes 75 to 83 gives the information for the 8-kbyte blocks (block 8 and block 9). for a description of this data, please refer to table 4.3.5. 16. the data in the 84th byte sent by the device is checksum data. this is the low-order 8-bit value in 2?s complement representation obtained by adding eight bits of transmit data in the fifth to the 83rd bytes not including the sign (ignoring overflow). 17. the received data in the 85th byte is the next operation command data.
2006-01-27 92fd54ai-45 tmp92fd54ai 4) auto chip erase & unprotect command (see table 4.3.47.) 1. the transmitted/received data in the first and second bytes are the same as for the ram transfer command. 2. the data received in the third byte is the operation command data. in this case it is auto chip erase & unprotect command data (40h). 3. the data in the fourth byte is the ack response data returned by the device for the operation command data in the third byte. the first, the device checks if the received data in the third byte contains an error. if a receive error is found, the device returns the ack response data for, communication error (bit 3) x8h and waits for the next operation command (third byte). the four high-order bits of the returned ack response data are undefined. (they are the four high-order bits of the immediately preceding operation command data.) next, if the data received in the third byte corresponds to one of the operation command values given in table 4.3.2, the device echoes back the received data (the ack response data for normal reception). in this case the data value 40h is echoed back and the program branches to the auto chip erase & unprotect processing routine. if the received data does not correspond to any operation command the device returns the ack response data for an operation command error (bit 0) x1h and waits for the next operation command (third byte). the four high-order bits of the returned ack response data are undefined. (they are the four high-order bits of the immediately preceding operation command data.) 4. the data in the fifth bytes sent by the device indicates whether collective erase has terminated normally. when collective erase has terminated normally, the device returns collective erase terminated normally code (4fh). if an erase error occurs, the device returns erase error code (4ch). 5. the data in the sixth bytes sent by the device are ack response data. when collective erase has terminated normally, the device returns collective erase ack response code (b1h). if an erase error occurs, the device returns erase error ack response code (b4h). 6. the data received as the seventh byte is the data value for the next operation command.
2006-01-27 92fd54ai-46 tmp92fd54ai 5) ack response data the boot program notifies the controller of the processing status by sending various codes. table 4.3.8 to table 4.3.101 show the ack response data returned by the device for each item of received data. the four high-order bits of the ack response data are a direct reflection of the four high-order bits of the operation command data. bit 3 indicates a receive error, and bit 0 indicates an operation command error, checksum error or password error. bits 1 and 2 are always 0. table 4.3.8 ack response data to data for determining the serial operation mode returned data meaning of data returned by the device 86h it is found that device can communicate in uart mode. table 4.3.9 ack response data to operation command data returned data meaning of data returned by the device x8h * 1 a receive error occurred in the operation command data. x1h * 1 undefined operation command data was received normally. 10h data was found to be a ram transfer command. 20h data was found to be a flash memory sum command. 30h data was found to be a product information read command. 40h data was found to be an auto chip erase & unprotect command. * 1: the four high-order bits are a direct reflection of the four high-order bits of the immediately preceding operation command data. table 4.3.10 ack response data to checksum data returned data meaning of data returned by the device 18h an error had occurred in the received data. 11h a checksum error or password error occurred. 10h the checksum was found to be the correct value. table 4.3.11 ack response data to auto chip erase & unprotect data returned data meaning of data returned by the device 4fh the erase operation has terminated normally 4ch the erase error occurred. b1h reconfirmation of erase operation b4h reconfirmation of erase error operation
2006-01-27 92fd54ai-47 tmp92fd54ai 6) determination of serial operation mode when communicating in uart mode, the co ntroller should transmit the data value 86h as the first byte at the desired baud rate. figure 4.3.3 data for determining the serial operation mode the boot program disables reception of the serial operation method recognition data (86h) received from the controller as the first byte after a reset and finds the durations of tab, tac and tad shown in figure 4.3.3 using the procedure shown in the flowchart in figure 4.3.4. as shown in the flowchart in figure 4.3.4, when the cpu detects a level change on the receive pin while monitoring the pin status, it latches the current timer value. for this reason, the timer values for tab, tac and tad are somewhat erroneous. also, if the baud rate is fast, the cpu may not be able to detect a level change on the receive pin. as shown in the flowchart in figure 4.3.5, the serial operation mode is determined by the relative magnitude of the durations tab and tcd when the receive pin level is low. when tab < tcd, the serial operation mode is found to be uart mode and the boot program determines from the duration of tad whether or not the baud rate can be automatically set. since the timer values for tab, tac and tad include some error, as mentioned earlier, if the baud rate is fast and the operating frequency slow, the timer values will not be long enough to enable the boot program to determine the serial operation mode correctly as intended. for example, it may be erroneously determined that the serial operation mode is not uart mode when in fact the controller intends to communicate in uart mode. to avoid this kind of problem, if the controller is trying to communicate in uart mode, a time-out time after transmission of the first byte of data should be set for the controller; if the data 86h cannot be received normally from the device within the time-out time, this can be used to determine that the device cannot communicate. uart (86h) tab point a point b point c point d bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 start stop tcd
2006-01-27 92fd54ai-48 tmp92fd54ai figure 4.3.4 serial operation mode reception flowchart initialize 16-bit timer 0 ( t1 = 8/f, counter cleared) set tb0rg1 value = 0xffff prescaler starts 16-bit timer 0 starts counting up point a stop operation (infinite loop) receive pin changed from high to low? yes yes yes start receive pin changed from low to high? latch and save timer value using soft capture (tab) receive pin changed from high to low? latch and save timer value using soft capture (tac) yes receive pin changed from low to high? latch and save timer value usin g soft ca p ture ( tad ) 16-bit timer 0 stops counting tac tad? back up tad value end yes point b point c point d no no no
2006-01-27 92fd54ai-49 tmp92fd54ai figure 4.3.5 flowchart for determination of serial operation mode tcd tad ? tac tab > tcd? start yes found to be uart mode error no
2006-01-27 92fd54ai-50 tmp92fd54ai 7) the password if the received operation command data is a ram transfer command (10h), the boot program checks the password. first, after echoing back the received operation command data (10h), the boot program checks the data (12 bytes) in the password area (addresses 08fef4h to 08feffh). next, the boot program checks the received data in bytes 5 to 16 (the password data) against the corresponding data in the flash memory. the relationship between the received data and the flash memory data which is compared with it is shown in table 4.3.5. unless all of 12 bytes of the data match, a password error is assumed to have occurred. in this case, the ack response returned for the checksum value in the 17th byte will signify a password error. table 4.3.12 relationship between data received and data in flash memory with which it is compared received data flash memory data for comparison 5th byte data at address 08fef4h 6th byte data at address 08fef5h 7th byte data at address 08fef6h 8th byte data at address 08fef7h 9th byte data at address 08fef8h 10th byte data at address 08fef9h 11th byte data at address 08fefah 12th byte data at address 08fefbh 13th byte data at address 08fefch 14th byte data at address 08fefdh 15th byte data at address 08fefeh 16th byte data at address 08feffh
2006-01-27 92fd54ai-51 tmp92fd54ai 8) calculating sum sum is word value which the boot program returns after summing the values of all the data bytes which it has read. the resulting sum is sent to the controller high-order byte first and low-order byte last. all the data in the flash memory (512 k-bytes) is included in the calculation of sum. the following example illustrates how the flash memory sum command calculates the sum value which is returned. example: 9) calculating checksum checksum is obtained by taking the 2?s-complement of the unsigned 8-bit value obtained by summing the values of the bytes received, ignoring any overflow. the checksum returned when the flash memory sum command or product information read command is executed is calculated in this way. the controller should also use this calculation method when transmitting checksum values. example: calculating checksum for flash memory sum command in this example the checksum value is found for when the high-order byte of sum is e5h and the low-order byte is f6h. first, the bytes are summed to yield an unsigned result. e5h + f6h = 1dbh take the 2s complement of the low-order byte of the resulting value as shown below. the result is the checksum value. consequently, the value 25h is sent to the controller. 0 ? dbh = 25h a1h b2h c3h d4h when the calculation is performed on the four data entries shown on the left, the value of sum is: a1h + b2h + c3h + d4h = 02eah hence the high-order data value for sum is 02h and the low-order data value is eah. therefore sum is sent to the controller as the value 02h followed by the value eah.
2006-01-27 92fd54ai-52 tmp92fd54ai (7) boot program general flowchart figure 4.3.6 shows an overall flowchart for the boot program. figure 4.3.6 overall flowchart for boot program initialize single boot program starts enter sio operation mode data prepare to enter operation command a ck response data ack response data & uart receive routine enter operation command data received normally receive error? ram transfer? a ck response data received data (10h) transmission routine (send 10h:ok) yes (10h) ram transfer processing processed normally? jump to ram processed normally ack response data ack response data 0x08 transmission routine (send x8h: receive error) sum? operation command error yes (20h) a ck response data received data (20h) ack response data ack response data | 0x01 transmission routine (send 20h:ok) transmission routine (send x1h: command error) sum processing error product information read? yes (30h) a ck response data received data (30h) transmission routine (send 30h: ok) product information read processing baud rate settin g ? set uart mode and set baud rate a ck response data received data (86huart) (send 86h) normal response stop operation cannot be set can be set erase? yes (40h) a ck response data received data (40h) transmission routine (send 40h: ok) auto chip erase & unprotect processing
92fd54ai-53 2006-01-27 tmp92fd54ai 4.4 programming/erasing flash memory during on-board programming the method used for controlling flash memory commands complies with jedec standards for standard e 2 proms. for this reason, during ram transfer operations in user boot mode or single boot mode the flash memory is programmed/erased by software commands executed by the cpu. the program for controlling this program/erase operation must be written in advance by the user. because the flash memory cannot be read while it is being programmed or erased, the program/erase control program must be placed in and executed from the internal ram or external memory after the device has entered user boot mode or after a ram transfer. 4.4.1 flash memory with a few exceptions, the functions for programming and erasing the flash memory are based on jedec-compliant commands. to program or erase the flash memory, enter a command to the flash memory using the cpu?s ld instruction. when a command is entered, the flash memory will automatically be programmed or erased internally. furthermore, to erase the flash memory, several different methods can be used: all the blocks can be erased together, each block can be erased individually. table 4.4.1 flash memory functions main functions description auto program automatically writes data and verifies written data in long word units. auto chip erase automatically erases and verifies all the blocks of the flash memory together. auto block erase automatically erases and verifies in units of blocks. hardware sequence flags monitoring flags such as a data polling or toggle bit flag help to confirm whether the flash memory is being programmed or erased. block protect block protect function prevents individual blocks of flash memory from being programmed or erased. as will be described later, in user boot mode or during ram transfer the method of address specification for operation commands differs from that for standard commands for reasons of interfacing with the cpu. also, unless otherwise stated, the flash memory is written to in units of 32 bits. when writing to flash memory, use 32-bit (long word) data transfer instructions. to enter commands, byte (8-bit) transfer instructions can be used.
92fd54ai-54 2006-01-27 tmp92fd54ai (1) block configuration single-chip single boot f80000h 010000h 64 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes 56 kbytes 56 kbytes 8 kbytes ffffffh 8 kbytes 08ffffh figure 4.4.1 flash memory block configuration (2) flash memory interface during on-board programming figure 4.4.2 is a conceptual diagram of the flash memory?s internal interface. note, however, that this diagram is only a schematic representation of the interface between the cpu and flash memory, and does not represent the actual circuit. figure 4.4.2 flash memory internal interface single-chip mode: f80000h to ffffffh single-boot mode: 010000h to 08ffffh decoder operation mode flash memory dq31 to dq0 d31 to d0 a31 to a17 a16 to a 2 ad14 to ad0 cpu ce we oe w r rd rdy/bsy rese t cpu rese t (512 kb) register
92fd54ai-55 2006-01-27 tmp92fd54ai (3) basic operation essentially the flash memory on the tmp92fd54ai has the following two modes of operation: ? mode in which data is read from memory (read mode) ? mode in which memory data is automatically erased/rewritten (auto operation mode) auto operation mode can be entered from read mode by the execution of a command sequence. in auto operation mode no data can be read from the flash memory. 1) read to read data, set the flash memory to read mode. the flash memory is automatically placed in read mode immediately after power-on, after the cpu is reset or when auto operation is terminated normally. if auto operation is terminated abnormally, or if you want to return to read mode from another mode, either use the read/reset command (software reset) or a hardware reset. these are described below. 2) writing commands the method used for controlling flash memory commands complies with jedec standards for standard e2proms. to write to the command register, execute a command sequence on the flash memory. when the flash memory has latched the input address and data into the command register, the program will executes the instruction (see tables 4.4.3 and 4.4.4). except for the fourth read cycle of a read/reset and for the fourth write cycle of an auto program only dq0 to dq7 are used to enter commands. commands can therefore be entered in byte units. if you want to cancel command entry in the middle of a command sequence, enter the reset command. on accepting the reset command, the flash memory resets the command register and enters read mode. likewise, if an erroneous command sequence is entered, the flash memory resets the command register and enters read mode. 3) reset ? read/reset command (software reset) when auto operation terminates abnormally, the flash memory does not automatically re-enter read mode. in this case use the read/reset command to return the flash memory to read mode. likewise, to cancel command entry in the middle of a command sequence, use the read/reset command to clear the contents of the command register. ? hardware reset as shown in figure 4.4.2, the flash memory has a reset input of its own. this input is connected to the cpu?s reset signal. hence, if the cpu is reset because the device?s reset input pin is pulled low (vil) or because the watchdog timer has overflowed, the current flash memory operation, whether a read operation (write or erase), will stop and the device will either remain in, or re-enter, read mode.
92fd54ai-56 2006-01-27 tmp92fd54ai also, if auto operation terminates abnormally or if the mode which has been set is cleared by the issuing of a command, the device will re-enter read mode due to the cpu being reset. note that if the device is halted by a hardware reset during auto operation, the flash memory data cannot be rewritten correctly. in this case it is necessary to rewrite the data. for details of the cpu?s reset operation, please refer to section 4.2.1, reset operation . after being reset by a designated reset input, the cpu reads reset vector data from the flash memory and starts post-reset operation. 4) auto program writing to the flash memory involves changing the contents of cells containing 1 to 0. you cannot change 0 to 1. the only way to write 1 to a cell is to erase all the cells. in user boot mode or during ram transfer, data is written to the flash memory in units of 32 bits (long words). auto program operation is begun when a program address and program data (in units of long words) are latched in the fourth bus write cycle of the command cycle. auto programming starts when the flash memory has latched the program data. since data is written in units of 32 bits, the program address must be incremented by 4. once program operation has begun, programming and program verification are automatically performed inside the chip. the status of an auto program operation can be checked by monitoring the hardware sequence flags (see table 4.4.6). during auto program operation, the device will not accept any command sequences input. to stop operation, use a hardware reset. note that if operation is interrupted, data cannot be written to the flash memory correctly . data cannot be written to addresses within a protected block. if this is attempted, the device will not execute auto program but will enter read mode. if auto program terminates normally, the device will automatically re-enter read mode. if auto program terminates in error, the flash memory will be locked into that mode and will not re-enter read mode. this status can be confirmed by inspecting the hardware sequence flag. to return to read mode, it is necessary to reset the flash memory or the device using the reset command or a hardware reset. in this case, because a write to the protected block address generated an error, it is recommended that the block which contains the bad address not be used or that the device itself not be used. 5) auto chip erase auto chip erase operation starts after the sixth bus write cycle of the command cycle has ended. once it has started, all flash memory addresses inside the chip are automatically programmed to 0; this is followed by the execution of erase and erase verify. the status of an auto chip erase operation can be checked by monitoring the hardware sequence flags (see table 4.4.5). during an auto chip erase operation, the device cannot accept any command sequences input. to stop operation, use a hardware reset. note that if operation is interrupted, data cannot be erased correctly and hence the auto chip erase must be re-executed.
92fd54ai-57 2006-01-27 tmp92fd54ai protected blocks, if any, cannot be erased. if all blocks are protected, the device will not execute auto chip erase but will enter read mode. in this case, the deletion operation other block of the following number of the protected block will be excuted. if auto chip erase terminates normally, the device will automatically re-enter read mode. if auto chip erase terminates in error, the flash memory will be locked in that mode and will not re-enter read mode. the status can be checked by inspecting the hardware sequence flag. to return to read mode, it is necessary to reset the flash memory or the device using the reset command or a hardware reset. in this case it will be impossible to detect which block generated the error. therefore, it is recommended that the bad block be located using the block erase function and that henceforth use the bad block not be used. 6) auto block erase an auto block erase starts the erase hold time after the sixth bus write cycle of the command cycle has ended. once it has started, all flash memory addresses in the selected block are automatically programmed to 0; this is followed by the execution of erase and erase verify. if any command sequence other than an auto block erase is entered during the erase hold time, the flash memory will be reset and will enter read mode. the status of an auto block erase operation can be checked by monitoring the hardware sequence flags (see table 4.4.6). during an auto block erase operation, the device cannot accept any command sequences input. to stop operation, use a hardware reset. note that in this case, data cannot be erased correctly, and hence the auto block erase must be re-executed. protected blocks, if any, cannot be erased. if all blocks are protected, the device will not execute auto block erase but will enter read mode. if auto block erase terminated in error, the flash memory will be locked in that mode and will not re-enter read mode. the status can be checked by inspecting the hardware sequence flag. to return to read mode, it is necessary to reset the flash memory or the device using the reset command or a hardware reset.
92fd54ai-58 2006-01-27 tmp92fd54ai 7) auto block protect auto block protect allows individual blocks to be protected from being written or erased. the table below shows the relationship between protection status and the rewrite operation. table 4.4.2 block protection status and the rewrite operation protection status and operation executed result of executed operation execute program on protected block not programmed and automatically returns to read mode execute erase on protected block not erased and automatically returns to read mode execute chip erase when all blocks are protected not erased and automatically returns to read mode execute chip erase when any blocks are protected only the unprotected blocks are erased. upon completion, the flash memory automatically returns to read mode writing to the protect circuit is initiated by the address of the block to be protected in the sixth bus write cycle of the command sequence, and set data to ?70h?. (see figure 4.4.8) during automatic operation no other command sequence input can be accepted. to stop operation use a hardware reset. when it erases auto block protect, use auto chip erase & unprotect command. (see table 4.4.3) in this case it erases all auto block protect and all blocks of the flash memory. 8) verify block protect verify block protect is used to check whether or not blocks are protected. enter the address of the block you want to check in the fourth bus read cycle of the command sequence. at this time, specify an address where a3 = a6 = 0, a4 = 1, and read the selected block in units of long words. if the block is protected, the data returned will be 00000001h. conversely, if the block is unprotected, the data returned will be 00000000h. to continue verifying the protection of other blocks, it is only necessary to repeating the fourth bus read cycle so as to read out data from each block. change the block address as desired and read the data out in long words. to return to flash memory read or any other command input after the verify block protect has been completed, it is necessary to issue a read/reset command or a hardware reset. 9) hardware sequence flags (see table 4.4.6) the status of automatic execution of operations on flash memory can be checked by inspecting the hardware sequence flags. during automatic operation data can be read out with the same timing as that of read mode. the flash memory automatically returns to read mode after automatic operation has finished. during automatic execution it is possible to monitor the operating status by inspecting the hardware sequence flags. after automatic operation has finished, the operating status can be confirmed by checking the read data to see that it matches the cell data. to inspect the hardware sequence flags during an auto program operation, specify the same address as the one which has been set by the rewrite routine (in which a0 = a1 = 0) at the same time as reading out the flag. also, to inspect the hardware sequence flags during an auto erase operation, specify an address in which a0 = a1 = 0 at the same time as reading out the flag.
92fd54ai-59 2006-01-27 tmp92fd54ai ? dq7 (data polling) the data polling function allows confirmation of the status of automatic operations on flash memory. data polling output begins after the last bus write cycle of an automatic operation command sequence has ended. during an auto program operation the data written to dq7 is output after being inverted. after an auto program operation, the cell data for dq7 itself is output so that the operation status can be identified by reading dq7. during an auto erase operation the data 0 is output on dq7; after an auto erase operation the data 1 (the cell data) is output on dq7. if an automatic operation resulted in an error, dq7 will continue to output the data it held during the automatic operation. therefore, this data can be used in combination with the value on dq5 (the internal timer-out) to determine whether failure has occurred (see figure 4.4.6). since the flash memory releases the address latch on completion of operation, to read out data it is necessary to specify either the address to which data has been written or the address of any unprotected erased block. ? dq6 (toggle bit) the toggle bit function, same as the data polling function, allows confirmation of the status of automatic operations on flash memory. the toggle output begins after the last bus write cycle of an automatic operation command sequence has ended on dq6. every read cycle, output reciprocally 0 and 1. if an automatic operation resulted in an error, dq6 will continue to output the data it held during the automatic operation. therefore, this data can be used in combination with the value on dq5 (the internal timer-out) to determine whether failure has occurred (see figure 4.4.6). ? dq5 (internal time-out) normally when automatic operation is in progress, the flash memory outputs 0 on dq5. if the automatic operation exceeds the flash memory?s internal time-out period, the dq5 output will change state to 1. this indicates that automatic operation did not terminate normally and suggests that the flash memory may be faulty. furthermore, since the flash memory can have its cells changed from data 1 to data 0 in program mode, but cannot have its cells changed from data 0 to data 1, if an attempt is made to write a data 1 to a data 0 cell, the device will not be able to write data correctly within the predetermined time. as a result, the device will output a 1 on dq5, just as if the flash memory were found to be faulty. in this case the value on dq5 is not indicating that the flash memory is faulty, but that an attempt to perform an invalid operation was made. if automatic operation did not terminate normally, the flash memory will be locked and will not re-enter read mode. therefore, reset the flash memory using the reset command. ? dq3 (block erase timer) auto block erase starts the block erase hold time after the sixth bus write cycle of the command cycle has ended. the flash memory outputs a 0 on dq3 during the block erase hold time and outputs a 1 when it starts an erase operation.
92fd54ai-60 2006-01-27 tmp92fd54ai 10) flash status register this is an 8-bit register which serves purposes of a flash memory status monitor. flash status register 7 6 5 4 3 2 1 0 bit symbol - - - - - r/bsy - - read/write r/w r/w r/w r/w r after reset 0 0 0 0 - 1 - - flsr (16eh) function set to 0. set to 0. set to 0. set to 0 . ready /busy flag 0:busy (auto operation in progress) 1:ready (auto operation finished) figure 4.4.3(1) flash status register bit 2: ready/busy flag bit the device has a rdy/bsy output which enables the status of automatic operation to be recognized by the host in programmer mode. this bit is used to monitor the rdy/bsy output from the cpu. when automatic operation is being performed on the flash memory, this bit outputs a 0, indicating that the flash memory is busy. when automatic operation has finished, it will output 1 and the flash memory will be ready to accept the next command. if automatic operation results in error, this bit will continue to output 0. the bit is reset to 1 by a hardware reset. the bit outputs 0 starting from completion of the last bus write cycle of the automatic operation command sequence. for an auto block erase, however, it starts outputting 0 the erase hold time after the said cycle has ended. if this bit = 0, no command sequence input can be accepted. 11) flash security write enable register this is an 8-bit register which allows to enable auto chip erase & unprotect command. flash security write enable resister 7 6 5 4 3 2 1 0 bit symbol - - - - - - - - read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 fswe (16bh) function c9h:auto chip erase & unprotect command enable code others: auto chip erase & unprotect command disable code figure 4.4.3(2) flash security write enable register pleas write it in the fswe register when you execute the program with ram.
92fd54ai-61 2006-01-27 tmp92fd54ai (4) command sequence list table 4.4.3 flash memory access by internal cpu 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus read/write cycle 5th bus write cycle 6th bus write cycle command sequence number of bus cycles addr. data addr. data addr. data addr. data addr. data addr. data read/reset 1 xxxx0h f0h read/reset 3 xaaa8h aah x5554h 55h xaaa8h f0h ra rd auto program 4 xaaa8h aah x5554h 55h xaaa8h a0h pa pd auto chip erase 6 xaaa8h aah x5554h 55h xaaa8h 80h xaaa8h aah x5554h 55h xaaa8h 10h auto block erase 6 xaaa8h aah x5554h 55h xaaa8h 80h xaaa8h aah x5554h 55h ba 30h auto block protect 6 xaaa8h aah x5554h 55h xaaa8h 9ah xaaa8h aah x5554h 55h ba 70h verify block protect 4 xaaa8h aah x5554h 55h xaaa8h 90h bpa bd auto chip erase & unprotect *1 6 xaaa8h aah x5554h 55h xaaa8h 80h xaaa8h aah x5554h 55h xaaa8h 10h note: there must be an interval of at least two instructions between each bus cycle. *1 when this command is operated, be sure to set fswe. the addresses to be accessed from the cpu are shown below. table 4.4.4 relationship between addresses command address cpu addresses: a23 to a0 addr. a23 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0000h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 aaa8h 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 5554h flash memory address area 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 (5) additional explanation ? f0h, aah, 55h, a0h, 80h, 10h, 30h: command data. write data in units of bytes. ? ra: read address rd: read data output ? pa: program address pd: program data input ? ba: block address (ba0~ba6) ? bpa: verify block protect address ? bd: block protect data write data to addresses which are divisible by 4 in units of long word please refer to part 8), entitled v erify block protec t , on page 58 of section 3.4.1 (3), basic operation . if the block is protected, the data 0x0000 _ 0001 will be returned; if it is not protected, the data 0x0000_0000 will be returned. please refer to table 4.4., block erase addresses.
92fd54ai-62 2006-01-27 tmp92fd54ai table 4.4.5 block erase addresses address area block user boot mode single boot mode size ba0 f80000h to f8ffffh 010000h to 01ffffh 64kbite ba1 f90000h to f9ffffh 020000h to 02ffffh 64kbite ba2 fa0000h to faffffh 030000h to 03ffffh 64kbite ba3 fb0000h to fbffffh 040000h to 04ffffh 64kbite ba4 fc0000h to fcffffh 050000h to 05ffffh 64kbite ba5 fd0000h to fdffffh 060000h to 06ffffh 64kbite ba6 fe0000h to fedfffh 070000h to 07dfffh 56kbite ba7 fee000h to ffbfffh 07e000h to 08bfffh 56kbite ba8 ffc000h to ffdfffh 08c000h to 08dfffh 8kbite ba9 ffe000h to ffffffh 08e000h to 08ffffh 8kbite enter an address within the address area of the block to be selected. this should be an address for which a0 = a1 = 0. example: to select ba0 in user boot mode, enter any address in the area f80000h to f8ffffh. table 4.4.6 hardware sequence flags status d7 (dq7) d6 (dq6) d5 (dq5) d3 (dq3) auto program /d7 toggle 0 0 auto erase (during erase hold time) 0 toggle 0 1 auto protect program * toggle 0 0 automatic operation in progress auto chip erase & unprotect * toggle 0 1 auto program /d7 toggle 1 0 auto erase 0 toggle 1 1 auto protect program * toggle 1 0 time-out (automatic operation failed) auto chip erase & unprotect * toggle 1 1 read complete normally cell data cell data cell data cell data note: the settings for d31 to d8, d4 and d2 to d0 are ?don?t care?.
92fd54ai-63 2006-01-27 tmp92fd54ai (6) flowchart figure 4.4.4 auto program auto program command sequence (see the flow shown below.) last address? start no data polling, toggle bit (read out in units of long words) yes auto program finished address = address + 4 (in units of long words) a uto program command sequence (address/command) xaaa8h/aah x5554h/55h xaaa8h/a0h program address (a1, a0 = 0)/ program data (in units of long words)
92fd54ai-64 2006-01-27 tmp92fd54ai figure 4.4.5 auto erase auto erase command sequence (see the flow shown below) start data polling, toggle bit (read out in units of long words) auto erase finished a uto chip erase command sequence (address/command) xaaa8h/aah x5554h/55h xaaa8h/80h xaaa8h/aah x5554h/55h xaaa8h/10h a uto block erase command sequence (address/command) xaaa8h/aah x5554h/55h xaaa8h/80h xaaa8h/aah x5554h/55h block address / 30h
92fd54ai-65 2006-01-27 tmp92fd54ai figure 4.4.6 dq7 data polling figure 4.4.7 dq6 toggle bit read long word addr. = va dq5 = 1 ? start y es dq7 = data ? read long word addr. = va no dq7 = data ? terminates abnormally terminates normally y es y es no no read long word addr. = va dq5 = 1 ? start y es dq6 = data ? read long word addr. = va no dq6 = data ? terminates abnormally terminates normally y es y es no no va: the address of writing data (auto program) the address of any flash memory address.(auto chip erase) the address of selected bloc k address ( auto block erase )
92fd54ai-66 2006-01-27 tmp92fd54ai figure 4.4.8 auto block protect xaaa8h/aah start x5554h/55h xaaa8h/9ah xaaa8h/aah x5554h/55h block address/70h block protect finished
92fd54ai-67 2006-01-27 tmp92fd54ai figure 4.4.10 auto chip erase & unprotect xaaa8h/aah x5554h/55h xaaa8h/80h xaaa8h/aah x5554h/55h xaaa8h/10h start
2006-01-27 92fd54ai-68 tmp92fd54ai 5. electrical characteristics 5.1 absolute maximum ratings parameter symbol rating unit power supply voltage v cc5 -0.5 to 6.0 v input voltage v in -0.5 to vcc5+0.5 v output current(total) iol 100 ma output current(total) ioh -100 ma power dissipation(ta=85degree c) p d 600 mw soldering temperature(10s) t solder 260 degree c storage temperature t stg -65 to 150 degree c operation temperature -40 to 85 operation temperature (flash program / erase) t opr 0 to 70 degree c the number of write erase cycles n ew 100 cycle note: the absolute maximum ratings are rated values that must not be exceeded during operation, even for an instant. any one of the ratings must not be exceeded. if any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. thus, when designing products that include this device, ensure that no absolute maximum rating value will ever be exce eded.
2006-01-27 92fd54ai-69 tmp92fd54ai 5.2 dc electrical characteristics vcc5 =4.5v to 5.25v / fc = 16 to 20mhz / ta = -40 to 85 degree c parameter symbol condition min max unit supply voltage v cc5 4.5 5.25 v input low voltage p00 to p07(d0 to 7) pg0 to pg7 pl0 to pl3 v il0 -0.3 0.8 v input low voltage p00 to p07(port) p40 to p47 v il1 -0.3 0.3*vcc5 v input low voltage int0 nmi reset p70, p71, p73 to p75 pc0 to pc5 pd0 to pd7 pf0 to pf7 pm0 to pm4 v il2 -0.3 0.25*vcc5 v p72, pn0 to pn6 v il6 -0.3 0.3*vcc5 v input low voltage am0 to am1 test0 to test1 v il3 -0.3 0.3 v input low voltage x1, xt1 (crystal) v il4 * vcc3 = 3.3v -0.3 0.2*vcc3 v input low voltage xt1 (cr) v il5 * vcc3 = 3.3v -0.3 0.2*vcc3 v input high voltage p00 to p07(d0 to 7) pg0 to pg7 pl0 to pl3 v ih0 2.2 vcc5+0.3 v input high voltage p00 to p07 p40 to p47 v ih1 0.7*vcc5 vcc5+0.3 v input high voltage int0 nmi reset p70, p71, p73 to p75 pc0 to pc5 pd0 to pd7 pf0 to pf7 pm0 to pm4 v ih2 0.75*vcc5 vcc5+0.3 v p72, pn0 to pn6 v ih6 0.7*vcc5 vcc5+0.3 v input high voltage am0 to am1 test0 to test1 v ih3 vcc5-0.3 vcc5+0.3 v input high voltage x1, xt1 (crystal) v ih4 * vcc3 = 3.3v 0.8*vcc3 vcc3+0.3 v input high voltage xt1 (cr) v ih5 * vcc3 = 3.3v 0.7*vcc3 vcc3+0.3 v
2006-01-27 92fd54ai-70 tmp92fd54ai parameter symbol condition min max unit output low voltage v ol i ol = 3.0ma 0.4 v v oh0 i oh = -400ua 2.4 v oh1 i oh = -100ua 0.75*vcc5 v oh2 i oh = -20ua 0.9*vcc5 output high voltage v ohn i oh = -200ua, pf6(tx) pin 0.82*vcc5 v input leakage current i li 0.0 Q vin Q vcc5 0.02(typ.) +/- 5 ua output leakage current i lo 0.2 Q vin Q vcc5-0.2 0.05(typ.) +/- 10 ua operating current (single chip)* i cc5 v cc5 =5.25v , x1=10mhz(internal 20mhz) 80(typ) 100 ma i cc5idle2 idle2 mode v cc5 =5.25v, x1=10mhz(internal 20mhz ) 90 i cc5idle1 idle1 mode v cc5 =5.25v, x1=10mhz(internal 20mhz) 30 ma i cc5idle3 idle3 mode v cc5 =5.25v, ta = -40 to 85 degree c v cc5 =5.25v, ta = -10 to 55 degree c 220 140 ua operating current (stand-by) i cc5stop stop mode v cc5 =5.25v, ta = -40 to 85 degree c v cc5 =5.25v, ta = -10 to 55 degree c 200 120 ua stand-by voltage v stb5 v cc3 < v cc5 , v ih1 2006-01-27 92fd54ai-71 tmp92fd54ai vcc5 =4.5v to 5.25v / fc = 16 to 20mhz / ta = -40 to 85 degree c flash single-boot mode ( ta=0 to 70 degree c during programming or erasing of flash memory) parameter symbol condition min max unit mean operating current (during reading) i ddo1 80 100 ma mean operating current (during programming) i ddo2 D 100 ma mean operating current (during erasing) i ddo3 fc = 20 mhz D 110 ma standby current i dds v cc5 =5.25v, ta = -40 to 85 degree c v cc5 =5.25v, ta = -10 to 55 degree c D 200 120 ua note: precautions when programming/erasing flash memory 1) in on-board programming mode (single-boot mode or user boot mode), inhibit all interrupts including nmi to allow the highest priority for program/erase operations. 2) to rewrite data in already programmed addresses, execute an auto erase before executing auto program.
2006-01-27 92fd54ai-72 tmp92fd54ai 5.3 ac characteristics read cycle vcc5=4.5 to 5.25v 5%, ta=--40 to 85 degree c no. parameter symbol min max 20mhz 16mhz unit 1 osc period (x1/x2) t osc 100 125 100 125 ns 2 system clock period (=t) t cyc 50 62.5 50 62.5 ns 3 clk low width t cl 0.5 t-15 10 16 ns 4 clk high width t ch 0.5 t-15 10 16 ns 5-1 a0 to a23 valid d0 to d7 input 0wait t ad 2.0 t-50 50 75 ns 5-2 a0 to a23 valid d0 to d7 input 1wait t ad3 3.0 t-50 100 138 ns 6-1 rd fall d0 to d7 input 0wait t rd 1.5 t-45 30 49 ns 6-2 rd fall d0 to d7 input 1wait t rd3 2.5 t-45 80 111 ns 7-1 rd low width 0wait t rr 1.5 t-20 55 74 ns 7-2 rd low width 1wait t rr3 2.5 t-20 105 136 ns 8 a0 to a23 valid rd fall t ar 0.5 t-20 5 11 ns 9 rd fall clk fall t rk 0.5 t-20 5 11 ns 10 a0 to a23 valid d0 to d7 hold t ha 0 0 0 ns 11 rd rise d0 to d7 hold t hr 0 0 0 ns 12 a0 to a23 valid port input t apr 2.0 t-120 -20 5 ns 13 a0 to a23 valid port hold t aph 2.0 t 100 125 ns 14 wait set-up time t tk 15 15 15 ns 15 wait hold time t kt 5 5 5 ns write cycle vcc5=5.0v 5%, ta=--40 to 85 degree c no. parameter symbol min max 20mhz 16mhz unit 1 osc period (x1/x2) t osc 100 125 100 125 ns 2 system clock period (=t) t cyc 50 62.5 50 62.5 ns 3 clk low width t cl 0.5 t-15 10 16 ns 4 clk high width t ch 0.5 t-15 10 16 ns 5-1 d0 to d7 valid wr rise 0wait t dw 1.25 t-35 28 43 ns 5-2 d0 to d7 valid wr rise 1wait t dw3 2.25 t-35 78 106 ns 6-1 wr low width 0wait t ww 1.25 t-30 33 48 ns 6-2 wr low width 1wait t ww3 2.25 t-30 83 111 ns 7 a0 to a23 valid wr fall t aw 0.5 t-20 5 11 ns 8 wr fall clk fall t wk 0.5 t-20 5 11 ns 9 wr fall a0 to a23 hold t wa 0.25 t-5 8 11 ns 10 wr fall d0 to d7 hold t wd 0.25 t-5 8 11 ns 11 a0 to a23 valid port output t apw 2.0 t+70 170 195 ns 12 wait set-up time t tk 15 15 15 ns 13 wait hold time t kt 5 5 5 ns 14 rd rise d0 to d7 output t rdo 1.25 t-35 20 26 ns ac condition ? output : d0 to d7, a0 to a7, a8 to a15, a16 to a23, rd, wr high 2.0v, low 0.8v, cl=50pf others high 2.0v, low 0.8v, cl=50pf ? input : d0 to d7 high 2.4v, low 0.45v, cl=50pf others high 0.8 vcc5, low 0.2 vcc5
2006-01-27 92fd54ai-73 tmp92fd54ai (1) read cycle (0 wait) note : the phase relation between x1 input signal and the other signals is unsettled. the timing chart above is an example . x1 cl k (fc) wai t a0 to a23 cs rd d0 to d7 port inpu t t osc t cyc t cl t ch t tk t kt t ad t ar t rk t rr t rd data input port input t apr t aph t hr t ha
2006-01-27 92fd54ai-74 tmp92fd54ai (2) write cycle (0 wait) note : the phase relation between x1 input signal and the other signals is unsettled. the timing chart above is an example. x1 cl k (fc) wai t a0 to a2 3 cs w r d0 to d 7 port outpu t t osc t cyc t cl t ch t tk t kt t aw t wk t ww t dw data output t apw t wa rd t wd t rdo
2006-01-27 92fd54ai-75 tmp92fd54ai (3) read cycle (1 wait) (4) write cycle (1 wait) cl k (fc) wai t a0 to a23 cs rd d0 to d7 t ad3 t rr3 t rd3 data input cl k (fc) wai t a0 to a23 cs w r d0 to d7 t ww3 t dw3 data output rd t rdo
2006-01-27 92fd54ai-76 tmp92fd54ai 5.4 ad conversion characteristics symbol parameter min typ max unit vrefh analog reference voltage( ) vcc5-0.2 vcc5 vcc5 vrefl analog reference voltage( ) vss5 vss5 vss5 avcc ad converter power supply voltage vcc5-0.2 vcc5 vcc5 avss ad converter ground vss5 vss5 vss5 avin analog input voltage vrefl vrefh v analog current for analog reference voltage =1 0.8 1.2 ma i ref =0 0.02 5 ua e t total error (excluding quantize error) 3.0 lsb note) ?lsb? is the unit which means the resolution of ad converter. (+/- 3 lsb = 3 * vcc/1024 = +/-15mv) 5.5 event counter (ti0, ti4, ti8, ti9, tia, tib) variable 20mhz 16mhz parameter symbol min max min max min max unit clock cycle t vck 8t+100 500 600 ns clock low width t vckl 4t+40 240 290 ns clock high width t vckh 4t+40 240 290 ns 5.6 serial channel timing (1) sclk input mode (i/o interface mode) variable 20mhz 16mhz parameter symbol min max min max min max unit sclk cycle t scy 16t 0.8 1.0 us output data sclk rise t oss t scy /2-4t -110 90 140 sclk rise output data hold t ohs t scy /2+2t 500 625 sclk rise input data hold t hsr 3t+10 160 197.5 sclk rise input data valid t srd t scy 800 1000 ns (2) sclk output mode (i/o interface mode) variable 20mhz 16mhz parameter symbol min max min max min max unit sclk cycle (programmable) t scy 16t 8192t 0.8 409.6 1.0 512 us output data sclk rise t oss t scy /2-40 360 460 sclk rise output data hold t ohs t scy /2-40 360 460 sclk rise input data hold t hsr 0 0 0 sclk rise input data valid t srd t scy /2-t -180 570 757.5 ns
2006-01-27 92fd54ai-77 tmp92fd54ai (3) sclk input mode (uart mode) (preliminary) variable 20mhz 16mhz parameter symbol min max min max min max unit sclk cycle t scy 4t + 20 220 270 sclk low level pulse width t scyl 2t + 5 105 130 sclk high level pulse width t scyh 2t + 5 105 130 ns 5.7 interrupt operation variable 20mhz 16mhz parameter symbol min max min max min max unit nmi,int0 low width t intal 4t 200 250 nmi,int0 high width t intah 4t 200 250 wuint0 to wuint7, int1 to int7 low width t intbl 8t+100 500 600 wuint0 to wuint7, int1 to int7 high width t intbh 8t+100 500 600 ns scl output data txd t hsr valid valid t srd 1 0 t ohs t sc y t oss input data rxd
2006-01-27 92fd54ai-78 tmp92fd54ai 5.8 serial bus interface 5.8 serial bus interface i2cbus-ac-spec table min max min max min max 1 scl clock frequency khz 0 400 0 100 0 fc/(2 n +8) 2 hold time (repeated) start condition. after this period, the first clock pulse is generated. hd sta ns 650 - 4500 - 2 n-1 /fc - 3 low period of the scl clock low ns 1300 - 4700 - 2 n-1 /fc - 4 high period of the scl clock high ns 600 - 4000 - (2 n-1 +8)/fc - 5 set-up time for a repeated start condition su sta ns 6 data hold time: for cbus compatible masters for i2c-bus devices hd da t ns 0 900 0 3450 0 6/fc 7 data set-up time su da t ns 100 - 250 - (2 n-1 -6)/fc - ? data set-up time (the case in the first bit after transfer ) su 1stda t (2 n-1 -12)/f c - 8 rise time of both sda and acl signals (*1) r ns - 300 (receive) - 1000 (receive) - 9 fall time of both sda and acl signals ns - 300 - 300 - 10 set-up time for stop condition su st o ns 950 - 4200 - ( 2 n-1 +12)/f c - 11 bus free time between a stop and start condition buf ns 12 capacitive load for each cus line c b pf 400 400 400 13 noise margin at the low level for each connected device (including hysteresis) v nl v 0.2v dd5 -0.2v dd5 -0.2v dd5 - 14 noise margin at the high level for each connected device (including hysteresis) v nh v 0.2v dd5 -0.2v dd5 - 0.2v dd5 - 15 pulse width of spikes which must be suppressed by the input filter t sp ns 0 50 n/a n/a n/a n/a note 1 all values referred to v ihmin and v ilmax levels. (fc= ) no parameter symbo l unit (fc=system clock) by software by software kh 100khz existing rate by software by software by software by software sda sc l low f hd:sta hd:dat r su:dat f high su:sta hd:sta sp su:sto r buf s sr p s s : start p :stop sr : restart su:1stdat i2bus clk ac spec : tr (transmitter selection ) vih sclk t-low tr t-high sck(0001 - 0110) 2*(n-1)/fc (2*(n-1)+8)/fc sck(1111) :100khz 100/fc 100/fc sck(1000) :400khz 32/fc 18/fc tr 0 to 2/fc 2/fc to 4/fc 4/fc to 6/fc 6/fc to 8/fc 8/fc to 10/fc ?. sck(0001 - 0110) t-r 0 4/fc 8/fc ?. sck(1111) :100khz t-r 0 4/fc 8/fc ?. sck(1000) :400khz t-r 0 2/fc 4/fc 6/fc 8/fc ?. t-period = t-low + t-r + t-high example: in the case of fc=20mhz, sck3,2,1,0=(0001), tr=200ns 1) tr=200ns so t-r=4/fc 2) t-period = 2*(n-1)/fc + 4/fc + (2*(n-1)+8)/fc =76/fc =3.8us *1)
2006-01-27 92fd54ai-79 tmp92fd54ai 5.9 serial expansion interface variable 20mhz symbol parameter min max min max unit t seclk seclk cycle 5t 40t 250 2000 ns t lead ss fall ? seclk 4t 200 ns t lag seclk ? ss rise 4t 200 ns t sckh seclk high pulse width t seclk /2-9 116 ns t sckl seclk low pulse width t seclk /2-9 116 ns t su input data set-up t seclk /4-10 52 ns t h input data hold t seclk /4 62 ns t v output data valid t seclk /4 62 ns t ho output data hold 0 0 ns a) sei master (cpha=0) ss seclk seclk miso mosi b) sei master (cpha=1) ss seclk seclk miso mosi lsb input bit 6 to 1 msb input lsb output bit 6 to 1 msb output t v t ho t h t su t seclk lsb output bit6 to 1 msb output lsb input bit6 to 1 msb input t v t ho t seclk t sckh t sckl t h t su
2006-01-27 92fd54ai-80 tmp92fd54ai c) sei slave (cpha=0) ss seclk seclk miso mosi d) sei slave (cpha=1) ss seclk seclk miso mosi 5.10 controller area network (can) variable 20mhz symbol parameter min max min max unit t cclk can clock period 2t 100 ns t p tx edge ? rx input 2tcclk-20 180 ns lsb input bit 6 to 1 msb input lsb output bit 6 to 1 msb output t h t ho t v t ho t sckl t sckh t lag t lead lsb input bit 6 to 1 msb input lsb output bit 6 to 1 msb output t h t su t v t su t lead t lag t sckl t sckh t p t x t p rx
2006-01-27 92fd54ai-81 tmp92fd54ai 5.11 voltage regulator voltage regurator vcc5 =4.5v to 5.25v / fc = 16 to 20mhz / ta = -40 to 85 degree c parameter symbol condition min. typ. max. unit. output voltage regout 3.0 D 3.6 v output current iro vin-regout=1.0v 0 D 150 ma iq iro Q 10 ua 30 50 100 a iq1 10 ua iro 100ma (ta=25 ) 15 250 800 a quiescent current iop iro=150ma 6 8 10 ma standby current is regen=0 (regulator only) D 0.1 0.2 a 0.5[ohm] Q esr Q 5.0[ohm] parameter symbol condition min. typ. max. unit. stabilization capactor cs cb=10uf, esr=4.7 0.1 D 10 f bypass capactor cb cs=10uf, esr=4.7 (cs>=cb) 0.1 D 10 f input capactor cin (note) cs=10uf, esr=4.7 4.7 D 22 f equivalent series resistor esr cs=10uf cb=0.1uf 0.5 D 5 0.5[ohm] Q esr Q 50[ohm] parameter symbol condition min. typ. max. unit. stabilization capactor cs cb=0.6uf, esr=47 0.1 D 10 f bypass capactor cb cs=10uf, esr=47 (cs>=cb) 0.6 D 10 f input capactor cin (note) cs=10uf, esr=47 4.7 D 22 f equivalent series resistor esr cs=10uf cb=0.6uf 0.5 D 50 0.5[ohm] Q esr Q 100[ohm] parameter symbol condition min. typ. max. unit. stabilization capactor cs cb=1.0uf, esr=100 0.1 D 10 f bypass capactor cb cs=10uf, esr=100 (cs>=cb) 1.0 D 10 f input capactor cin (note) cs=10uf, esr=100 4.7 D 22 f equivalent series resistor esr cs=10uf cb=1.0uf 0.5 D 100 note: recommend tantalum capacitor. tmp92fd54ai dvcc5 regou t regen dvss dvcc 3 open cin c s es r c b
tmp92fd54ai 2006-01-27 92fd54ai-82 6. points to note and restrictions 6.1 notation (1) the notation for built-in i/o registers is as follows register symbol example: trun01 denotes bit t0run of register trun01. (2) read-modify-write instructions (rmw) an instruction in which the cpu reads data from memory and writes the data to the same memory location in one instruction. example 1: set 3, (trun01); set bit3 of trun01. example 2: inc 1, (400h); increment the data at 400h. ? examples of read-modify-write instructions on the tlcs-900/h1 exchange instruction ex (mem), r arithmetic operations add (mem), r/# adc (mem), r/# sub (mem), r/# sbc (mem), r/# inc #3, (mem) dec #3, (mem) logic operations and (mem), r/# or (mem), r/# xor (mem), r/# bit manipulation operations stcf #3/a, (mem) res #3, (mem) set #3, (mem) chg #3, (mem) tset #3, (mem) rotate and shift operations rlc (mem) rrc (mem) rl (mem) rr (mem) sla (mem) sra (mem) sll (mem) srl (mem) rld (mem) rrd (mem) .
tmp92fd54ai 2006-01-27 92fd54ai-83 6.2 points to note (1) watchdog timer the watchdog timer starts operation immediately after a reset is released. when the watchdog timer is not to be used, disable it. (2) the stable time of the internal clock when releasing the external reset using ?built-in clock doubler? until the internal reset is released, the requiring time to stabilize the circuit is automatically set. see section 3.1.2 ?reset operation? for details. also when releasing standby mode in stop mode using an interrupt until the internal circuit starts the operation, the stable time of the oscillator is automatically input. see section 3.4 ?standby function (3) stop mode? for details. (3) undefined bit in the built-in i/o register when reading the undefined bit in the built-in i/o register, the undefined value is output. thus, when creating program, it should not be depending on this bit condition. (4) reserved address areas the 16 bytes area (fffff0h to ffffffh) cannot be used for it is reserved as internal area. if using emulator, optional 64 kbytes of 16m bytes area are used for control emulator. therefore, if using emulator, its area cannot be used. (5) pop sr instruction execute the pop sr instruction during di condition.
2006-01-27 92fd54ai-84 tmp92fd54ai 7. package package dimensions p-lqfp100-1414-0.50c 75 76 51 50 26 100 25 1 14.0 0.2 16.0 0.2 1.0 typ 1.0 typ 14.0 0.2 16.0 0.2 0.2 0.1 0.5 0.08 m 15.0 0.2 1.85 max 1.4 0.2 0.08 0.5 0.2 0~10 0.125 +0.1 -0.05 unit : mm 0.1 +0.15 -0.1

▲Up To Search▲

Price & Availability of TMP92FD54AIF

	To Download TMP92FD54AIF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .